Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1998-04-29
2001-02-06
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S778000
Reexamination Certificate
active
06184582
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor circuitry and devices.
BACKGROUND OF THE INVENTION
Intensive development efforts in communication technologies, as well as in other “high-technology” disciplines, is fueling a need for high performance semiconductor devices and circuits. For example, in the optical communications arena, the growth in dense wavelength division multiplexing is driving the development of complex opto-electronic circuits such as the electrooptic modulated laser (“EML”), which comprises, among elements, a laser, modulator and photodetector. See, for example, U.S. Pat. Nos. 5,548,607; 5,147,825; 5,543,353; 5,539,763, incorporated by reference herein.
The complexity of design that characterizes the EML, other optoelectronic circuits and devices, and, more generally, semiconductor circuitry, is reflected in the processes used to make them and circuit and device topography. With regard to processing, cost containment efforts for such complex devices have led to the development of “add-on” optical subassemblies and planar lightwave circuits that must be bonded to the “active” side of a complex device. As to topography, a complex device such as the EML may have both active and passive structures that extend beyond a base plane of the device, resulting in a varied topography.
By virtue of their “radical” topography, and the bonding operations to which they are exposed, such devices are subjected to pressure at critical areas, such as the active layers of an EML. Such pressure causes stresses that may directly result in device failure, or may cause damage that leads to reliability problems. As a result, process yields and device performance suffers. As such, a need exists for improved semiconductor circuitry, optoelectronic devices and the like that, while characterized by significant topographical variations, are markedly less susceptible to damage caused by the aforementioned bonding operations.
SUMMARY OF THE INVENTION
In accordance with the present teachings, “compliant standoffs” are disposed on a support surface of a semiconductor or hybrid semiconductor device or circuit (“semiconductor device”). Such compliant standoffs extend further from the support surface than active and/or passive structures associated with the functioning (“device-functional structures”) of the semiconductor device. Moreover, such compliant standoffs are laterally offset from device-functional structures. The “top” of such compliant standoffs (i.e., the end remote from the support surface) advantageously serves as a bonding surface at which additional structures, such as optical subassemblies, waveguides, lightwave circuits and the like (“auxiliary devices”), are attached to the semiconductor device.
Since the present compliant standoffs extend further from the support surface than the device-functional structures, the device-functional structures are protected from potentially damaging contact with the auxiliary devices (e.g., during bonding of such auxiliary devices to the semiconductor device). In addition, due to the lateral offset between the compliant standoffs and the device-functional structures, mechanical stresses imparted by contact with auxiliary devices are conducted to the support (e.g., wafer, etc.) rather than the device-functional structures. Moreover, bonding operations for attaching an auxiliary device to the semiconductor device impart thermally-induced stresses that are substantially dissipated by the compliant standoff. Such thermally-induced stresses might otherwise cause damage (i.e., cracks, etc.) in the semiconductor device leading to compromised performance and/or device failure.
The compliant standoffs advantageously comprise a three-layer structure including a compliant layer, a barrier layer, and a wetting layer. The compliant layer, which disperses thermal and mechanical stresses, is disposed on the support surface of a semiconductor device. The wetting layer, which is at the “top” of the compliant standoff, receives a bonding material, such as solder, by which the auxiliary device is bonded to the compliant standoffs. Sandwiched between the compliant layer and the wetting layer is a barrier layer that prevents the bonding material from diffusing into the compliant layer and/or the semiconductor device.
In some embodiments, the compliant standoffs advantageously comprise conductive materials such that, in conjunction with the use of several other layers, they may be placed in ohmic electrical contact with at least one active region of the semiconductor device.
REFERENCES:
patent: 5956235 (1999-09-01), Krege et al.
Coult David Gerald
Derkits, Jr. Gustav Edward
Segner Bryan Phillip
Breyer Wayne S.
DeMont Jason P.
DeMont & Breyer LLC
Lucent Technologies - Inc.
Potter Roy
LandOfFree
Article comprising a standoff complaint metallization and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Article comprising a standoff complaint metallization and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Article comprising a standoff complaint metallization and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2582067