Article comprising a mechanically compliant bump

Details Article comprising a mechanically compliant bump Article comprising a mechanically compliant bump

2001-01-17

2002-05-14

Niebling, John F. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S738000, C257S773000, C257S775000, C257S779000, C257S780000, C438S613000, C438S614000

Reexamination Certificate

active

06388322

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains generally to flip-chip bonding, and more particularly to a mechanically compliant bump for use in flip-chip bonding.
BACKGROUND OF THE INVENTION
“Flip-chip” and “flip-chip bonding” refer to an assembly and method wherein a chip is attached to a substrate, which is typically another chip or a circuit board, such that chip surface (the active area or I/O side) faces the substrate. See, generally, J. H. Lau,
Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies
(McGraw-Hill, ©2000).
Flip-chip bonding addresses two broad classes of problems. One pertains to traditional electronic packaging issues (hereinafter “packaging applications,”) such as how to increase packaging efficiency (e.g., cost considerations, performance considerations, etc.). The second pertains to how to integrate two dissimilar electronic devices, such as a photonics device to a silicon-electronics chip, to form a functionally unified device (hereinafter “chip-on-chip applications”).
For packaging applications, the two electronics parts being bonded together are usually a semiconductor chip and a circuit board. Compared to the alternative—face-up wire bonding technology—the application of flip-chip technology to electronics packaging provides higher packaging density (e.g., more input/output), potentially shorter leads, lower inductance, better noise control, smaller device footprints, a lower packaging profile and is well suited for use with area array technology.
A variety of interconnect materials and methods can be used in flip-chip bonding, including, for example, tape automated bonding, wire interconnects, isotropic and anisotropic conductive adhesives, bumps, and pressure contacts. Bumps are becoming the interconnection method of choice for a number of applications.
For packaging applications, the flip-chip bonding process with bumps comprises, in pertinent part, depositing a bump of metal on each of a plurality of contact pads that are disposed on the surface of the parts (more properly, on the surface of a wafer at this stage of the method). This step, referred to as “wafer bumping,” is performed using any of a variety of known techniques, including evaporation, electroplating, stencil printing and jet printing, to name a few. After deposition, the bump is heated to its melting temperature in a step called “reflow.” During reflow, the bump assumes a semi-spherical shape due to the surface tension of the metal. In a so-called “tacking” operation, the bumps on the two parts are aligned and then pressed together forming an assemblage of the two parts.
Even though tacking is performed below the melting point of the bumps, bonding does occur. But to assure electrical connection in a large percentage of the bonds, further processing is desirable. To that end, after tacking, the assemblage is heated to the melting temperature of the bumps. As the bumps melt in a second reflow step, they co-mingle or weld, forming sound electrical connections in high yield.
The bumps for packaging applications are relatively large (c.a., about 100 microns) because of limitations pertaining to forming reflowed bumps. Bump pitch (i.e., spacing between the bumps) is similarly large since reflow might otherwise cause bridging (i.e., flow of metal) between adjacent bumps.
For “chip-on-chip” applications, flip-chip bonding with bumps provides the only commercially practical solution, at least in some cases. For example, it is very inconvenient, using wire bonding, to integrate two-dimensional arrays of devices (e.g, a focal plane array chip containing detectors) to a silicon-electronics chip containing, for example, electronic read-out, driver and/or processing circuitry. The bump and bump pitch are typically much smaller (c.a., 10-20 microns) for chip-on-chip applications than for packaging applications to allow for maximum device density and maximum I/O, as is often necessary.
Typically, a photolithographic lift-off technique is used to form bumps for both packaging and chip-on-chip applications. This technique, well known in the art, is described briefly below in conjunction with
FIGS. 1-3
.
FIG. 1
depicts, via a cross-sectional view, wafer
100
with resist
104
deposited thereon. In this illustration, resist
104
has already been patterned to define a plurality of openings
106
that extend from resist upper surface
108
through to wafer surface
102
. Metal is deposited through opening
106
on surface
102
to form bumps
210
, as shown in FIG.
2
. Metal also deposits on resist upper surface
108
.
Opening
106
are wider near wafer surface
102
than at resist upper surface
108
, thereby creating tapered side-walls
212
. Tapering the side-walls in this fashion prevents metal from coating them. The prior art teaches that side-walls
212
must be substantially metal-free to allow resist-removing solvent to penetrate to wafer surface
102
via gap
214
.
FIG. 3
depicts wafer
100
with resist
104
(and the overlying metal) removed leaving bumps
210
.
Any type (e.g., composition, size, etc.) of metal bump can be formed using this technique, given sufficient consideration of the adhesion of the metal to the wafer. For chip-on-chip applications, a soft metal or low-temperature metal is typically used. For the purposes of this specification, the phrases “soft metal” and “low-temperature metal” mean metal(s) or metal alloys having a melting point less than about 400 ° C. Illustrative low temperature metals include, without limitation, indium compositions, and certain alloys of tin, bismuth and zinc.
There are several reasons why soft metals are used for chip-on-chip applications. First, the small bump size and pitch characteristic of chip-on-chip applications increase the likelihood that bridging might occur between adjacent bumps during reflow. Consequently, following tacking, the temperature is not raised to the melting point of the bumps. As such, all bonding occurs during tacking at sub-melting point temperatures. This sub-melting point bonding operation is referred to as thermo-compression bonding. Since temperatures are below the melting point of the bumps, thermo-compression bonding produces a relatively weak bond. The bumps used for chip-on-chip applications therefore comprise a low temperature metal to effect the best bond possible under low temperature conditions.
Second, in chip-on-chip applications, the two chips being joined typically comprise dissimilar materials having different coefficients of thermal expansion. To avoid excessive thermal stresses upon cooling that might result in bond breakage, the tacking operation is performed at relatively low temperature (less than 100° C.). So, again, given such temperature limitations, low temperature metals will effect the best bonds.
And there is a third reason why low melting point metals are traditionally used for flip-chip bonding. In particular, it is very difficult to bring two chips (or a chip and a circuit board) together in perfectly parallel relation for bonding. Consequently, for both packaging and chip-on-chip applications, the bumps must be mechanically compliant (i.e., deformable) to accommodate the greater pressures exerted on some of the bumps when two parts are brought together out of parallel alignment.
Table I depicts a yield plot of a chip containing 256 photodetectors that are bonded to a silicon electronics chip (a chip-to-chip application) using high-temperature metal (in this case, gold) bumps. For the purposes of this specification, a “high-temperature metal” means metal(s) and metal alloys having a melting point above about 400° C. Illustrative high-temperature metals include, without limitation, gold, silver and chromium. In Table I, an “x” signifies no electrical connection, indicating a defective bump-to-bump bond, and “c” signifies a sound electrical connection.
TABLE I
Yield Plot of Chip
C   C
C
C
C
C
X
C
X
X
X
X
X
X
X
X
C   C
C
C
C
C
C
X
C
X
X
X
X
X
X
X
C   C
C
C
C
C
X
C
X
X
X
X
X
X
X
X
C  &ensp

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