Arrays of two-transistor, one-capacitor dynamic random...

Details Arrays of two-transistor, one-capacitor dynamic random... Arrays of two-transistor, one-capacitor dynamic random...

2000-02-17

2001-07-03

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S230050, C365S051000, C365S063000

Reexamination Certificate

active

06256221

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to electronic memories and in particular to arrays of two-transistor, one-capacitor dynamic random access memory cells.
BACKGROUND OF THE INVENTION
There are numerous ways in which a dynamic random access memories (DRAMs) are traditionally constructed, using variations in process, circuit designs, and system architecture. By varying these parameters, various problems related to device size and performance can be addressed. None the less, all currently available DRAMs are generally based upon architectures which share the following disadvantageous characteristics.
First, the typical general purpose DRAM has a single data port for writing and reading data to and from addressed storage locations (“dual ported” DRAMs are available which provide two data ports, typically one random and one serial port, however, these devices are normally limited to special memory applications).
Second, data writes and reads are only made to a given array on a location by location (e.g. one bit, one byte, one word) basis and only during the array active cycle. Specifically, in a “random access mode”, an access (read or write) is made to a single location per row address strobe (/RAS) active cycle and in a “page mode” an access is made to a single location per column address strobe (/CAS) or master clock cycle of the row addressed during the given /RAS cycle. During the inactive cycle, the array is in precharge and no accesses can be made to that array.
Third, no method has generally been established to handle contention problems which arise when simultaneous requests for access are made to the same DRAM unit. Current techniques for handling contention problems depend on the DRAM and/or system architecture selected by the designer and range, for example, from “uniform memory-noncontention” methods to “non-uniform memory access” (NUMA) methods.
Similarly, the system architectures of personal computers (PC's) generally share a number of common features. For example, the vast majority of today's PC's are built around a single central processing unit (CPU), which is the system “master.” All other subsystems, such as the display controller, disk drive controller, and audio controller then operate as slaves to the CPU. This master/slave organization is normally used no matter whether the CPU is a complex instruction set computer (CISC), reduced instruction set computer (RISC), Silicon Graphics MIPS device or Digital Equipment ALPHA device.
Present memory and PC architectures, such as those discussed above, are rapidly becoming inadequate for constructing the fast machines with substantial storage capacity required to run increasingly sophisticated application software. The problem has already been addressed, at least in part, in the mainframe and server environments by the use of multiprocessor (multiprocessing) architectures. Multiprocessing architectures however are not yet cost effective for application in the PC environment. Furthermore, memory contention and bus contention are still significant concerns in any multiprocessing system, let alone in a multiprocessing PC environment.
Thus, the need has arisen for new memories for use in high speed and/or multiprocessing systems. Preferably, such memories should have a “transparent” precharge and/or multiple random access ports. Additionally, these memories should be capable of use in addressing memory contention problems, especially those occurring in multiprocessing systems.
SUMMARY OF THE INVENTION
According to one embodiment, a memory is disclosed which includes an array of rows and columns of memory cells. For each of the columns, first and second interdigitated bitlines are provided coupled to the memory cells of that column, the first bitlines having an end coupled to a sense amplifier at a first boundary of the array and the second bitline having an end coupled to a second sense amplifier at a second boundary of the array. Control circuitry is provided which precharges the first bitlines of the columns of the array substantially simultaneous to an access to the array through the second bitlines of selected columns of the array.
Interdigitated bitlines provide significant advantages. Among other things, the layout of the bitlines in the sense amplifiers is more efficient and the die size can consequently be reduced. Additionally, adequate spacing between simultaneously toggling bitline sets is maintained which helps reduce undesirable signal cross-coupling between bitlines.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.


REFERENCES:
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patent: 4896294 (1990-01-01), Shimizu et al.
patent: 5007022 (1991-04-01), Leigh
patent: 5010519 (1991-04-01), Yoshimoto et al.
patent: 5377142 (1994-12-01), Matsumura et al.
patent: 5781482 (1998-07-01), Sakata
IEEE Custon Integrated Circ. Confrence. 1988, “Transparent Refresh DRAM (TRED) Using Dual-Port DRAM Cell” pp. 431-434 by Sakurai, Nogami, Sawada & Iizuka.

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