Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-08-02
2002-01-15
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S030000, C438S155000
Reexamination Certificate
active
06338989
ABSTRACT:
CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 1999-31743, filed on Aug. 2, 1999, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor liquid crystal display (TFT-LCD) device, and more particularly, to an array substrate for use in a TFT-LCD device and a method of manufacturing the same.
2. Description of Related Art
In general, LCD devices includes upper and lower substrates with a liquid crystal layer interposed therebetween. The upper substrate has a color filter and a common filter. The lower substrate has gate lines arranged in a transverse direction, data lines arranged in a longitudinal direction perpendicular to the gate lines, thin film transistors (TFTs) as switching elements arranged near the cross portions of the gate and data lines, and pixel electrodes arranged on regions defined by the gate and the data lines. Each of the TFTs has a gate electrode, a source electrode, and a drain electrode. The gate electrode is extended from the gate line and the source electrode is extended from the data line. The drain electrode is electrically connected with the pixel electrode through a contact hole. The LCD device further includes a pad portion. The pad portion includes a plurality of gate pads and a plurality of data pads. The gate pads serve to apply signal voltages to the gate lines, and the data pads serve to apply data voltages to the data lines. The gate and data pads are beneficially located on a non-display area.
In order to form the array substrate, i.e., the lower substrate, processes such as depositing, photolithography, etching, and stripping are repeated several times. As the processes increase in number, the risk of damage to components, such as the gate and data line, by processing errors increase, resulting in inferior products and a high production cost.
To overcome the problems described above, the overall manufacturing process has been simplified from an early eight-mask process to a five-mask process. The conventional five-mask process is explained hereinafter with reference to the accompanying drawings.
FIG. 1
is a plan view illustrating an array substrate after a third mask step of the five-mask process is finished. As shown in
FIG. 1
, the array substrate includes a gate line
15
arranged in a transverse direction, a data line
24
arranged in a longitudinal direction perpendicular to the gate line
15
, a TFT “T” arranged near the crossing of the gate and data line
15
and
24
, and a pixel region defined by the gate and data lines
15
and
24
. The TFT “T” has a gate electrode
13
, a source electrode
19
and a drain electrode
20
. The gate electrode is a portion of the gate line
15
. The source electrode is extended from the data line
24
. The drain electrode
20
is spaced apart from the source electrode
19
. The TFT “T” further includes a channel area
22
. The array substrate further includes gate and data pads
17
and
23
. The gate pad connects with the gate line
15
, and the data pad
23
connects with the data line
24
. The array substrate further includes a storage capacitor “C”. As a first capacitor electrode, a portion
16
of the gate line
15
is used, and as a second capacitor electrode, a metal layer
25
is used. In other words, in order to form the storage capacitor “C”, the metal layer
25
, an insulating layer (not shown), and the portion
16
of the gate line
15
are stacked in a prescribed order.
FIG. 2
shows cross sectional views, taken along lines A—A and B—B of FIG.
1
.
FIG. 2
is useful for illustrating the manufacturing process up to the third mask step. First, a metal layer is deposited on a transparent substrate
21
and patterned into the line
15
, including the gate electrode
13
and the gate pad
17
, through a photolithography process using a first mask. The metal layer is beneficially made of a material selected from a group consisting of Al, Mo, W, Ta and the like. A first insulating layer
14
is deposited on the exposed surface of the substrate
21
, covering the gate electrode
13
, the gate line
15
and the gate pad
17
. The first insulating layer
14
is beneficially made of silicon nitride (SiNx) or silicon oxide (SiOx). Then, an intrinsic amorphous silicon layer and a doped amorphous silicon layer are sequentially deposited on the first insulating layer
14
and then patterned into a semiconductor layer
18
and an ohmic contact layer
27
using a second mask. Next, a conductive metal layer is deposited over the whole surface of the substrate
21
and then is patterned into the source electrode
19
, the drain electrode
20
, the data line
24
and the data pad
23
using a third mask. At the same time, a portion of the ohmic contact layer
27
over the channel area is etched so that spaced ohmic contact layers
27
a
and
27
b
are formed, and the second capacitor electrode
25
is formed in the form of an island. The conductive metal layer is beneficially of Cr or a Cr-alloy.
FIG. 3
is a plan view illustrating an array substrate completed by the conventional five mask steps, and
FIG. 4
is a cross sectional view, respectively, taken along lines A—A and B—B of FIG.
3
. Subsequently to
FIG. 2
, a second insulating layer
29
is deposited over the whole surface while covering the source electrode
19
, the data pad
23
, the data line
24
, and the second capacitor electrode
25
. The second insulating layer is then patterned using a fourth mask to form the gate pad contact hole
31
(see FIG.
3
), the drain contact hole
33
, and the source pad contact hole
37
. The gate pad contact hole
31
is formed on the gate pad
17
, the drain contact hole
33
is formed on the drain electrode
20
, and the data pad contact hole
37
is formed on the data pad
23
. Further, at the same time, a capacitor contact hole
35
is formed on the second capacitor electrode
25
. Then, a transparent conductive material layer is deposited over the whole surface while filling the contact holes. The transparent conductive material layer is then patterned using a fifth mask to form a pixel electrode
39
, a data pad terminal
40
, and a gate pad terminal
41
. The pixel electrode
39
is formed on the pixel region “P” (see
FIG. 1
) and contacts the drain electrode
20
through the drain contact hole
33
and the second capacitor electrode
25
through the capacitor contact hole
35
. The data pad terminal
40
electronically contacts the source electrode
19
through the data pad contact hole
37
. The gate pad terminal
41
contacts the gate pad
17
through the gate pad contact hole
31
. The transparent conductive material layer is beneficially made of indium tin oxide (ITO) or indium zinc oxide (IZO).
The manufacturing process of the TFT array substrate using the five mask steps is a big advance over the earlier eight mask steps. However, in the TFT-LCD device, process simplification is one of the most important parameters to lower the inferiority rate of products, lower the production cost, and to increase production yield. Therefore, there is a need for an improved method of manufacturing an array substrate for use in the TFT-LCD device.
SUMMARY OF THE INVENTION
To overcome the problems described above, the principles of the present invention provide for embodiments of an array substrate for use in a thin film transistor liquid crystal display (TFT-LCD) device which can be manufactured with a high production yield using a simplified method of manufacturing.
In order to achieve the above object, the present invention relates to a method of manufacturing an array substrate for use in a thin film transistor liquid crystal display device using only four mask steps. First, a first opaque conductive metal layer and a first transparent conductive metal layer are sequentially deposited on a substrate and then patterned using a first mask to form a gate line and a gate pad. The gate line is connected with the gate pad at end portions
Ahn Byung-Chul
Ha Young-Hoon
Kim Yong-Wan
Yoo Soon-Sung
Chaudhari Chandra
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
LandOfFree
Array substrate for use in liquid crystal display device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Array substrate for use in liquid crystal display device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Array substrate for use in liquid crystal display device and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2839757