Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2007-02-16
2009-06-02
Kebede, Brook (Department: 2894)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S149000, C257SE29151, C349S192000
Reexamination Certificate
active
07541223
ABSTRACT:
In an array substrate and an LCD apparatus having the same, the array substrate includes a signal line, a first insulating layer formed on the signal line, and a pixel electrode formed on the first insulating layer and overlapped with the signal line. The pixel electrode is electrically connected with the signal line so as to discharge a signal through the signal line. A second insulating layer is disposed between the pixel electrode and the first insulating layer, and includes an opening formed in an overlapped area of the pixel electrode and the signal line so as to partially expose the first insulating layer. Thus, the LCD apparatus may have an enhanced display quality.
REFERENCES:
patent: 5335102 (1994-08-01), Kanemori et al.
patent: 6746905 (2004-06-01), Fukuda
patent: 2004/0125332 (2004-07-01), Choi
Choo Kyo-Seop
Park Jin-Suk
Yang Yong-Ho
Yoon Joo-Sun
F. Chau & Associates LLC
Kebede Brook
Samsung Electronics Co,. Ltd.
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