Array protection devices and fabrication method

Details Array protection devices and fabrication method Array protection devices and fabrication method

1995-02-16

1996-06-04

Thomas, Tom

Fishing, trapping, and vermin destroying

437922, H01L 2182

Patent

active

055232531

ABSTRACT:
The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.
Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

REFERENCES:
patent: 4536949 (1985-08-01), Takayama et al.
patent: 4602420 (1986-07-01), Saito
patent: 4853758 (1989-08-01), Fischer
patent: 5285099 (1994-02-01), Carruthers et al.

Affiliated with

Also associated with

Rating

Array protection devices and fabrication method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Array protection devices and fabrication method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Array protection devices and fabrication method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-383043