Array padding for higher memory throughput in the presence of di

Details Array padding for higher memory throughput in the presence of di Array padding for higher memory throughput in the presence of di

1996-08-23

2000-03-21

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711 5, 711173, 711150, 36523003, G06F 1206

Patent

active

06041393&

ABSTRACT:
An array padding technique is described that increases memory throughput in the presence of dirty misses. The technique pads arrays so that the starting addresses of arrays within a target loop are separated by P memory banks where P is a rounded integer equal to the number of memory banks divided by the number of arrays. The number of banks of separation can be incremented or decremented by 1 to also avoid path conflicts due to the sharing of buses in a typical hierarchical memory subsystem.

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