Array of transistors with low voltage collector protection

Details Array of transistors with low voltage collector protection Array of transistors with low voltage collector protection

2002-06-11

2004-08-03

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S341000, C257S343000

Reexamination Certificate

active

06770935

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices, and more particularly, to semiconductor transistors including an LDMOS (lateral double-diffused metal oxide semiconductor) device.
BACKGROUND OF THE INVENTION
Battery-operated electronic systems such as notebook personal computers, personal digital assistants, and wireless communication devices often use power MOS (metal oxide semiconductor) devices as low on-resistance electronic switches for distributing battery power. For battery-operated application, low on-resistance can be particularly important to ensure as little power consumption to the battery as possible. This ensures long battery life.
DMOS devices are “double diffused” MOS devices. A DMOS device is characterized by a source region and a back gate region, which are diffused at the same time. The back gate region is sometimes referred to as a Dwell (double diffused well) region. The channel is formed by the difference in the two diffusions, rather than by separate implantation. DMOS devices have the advantage of decreasing the length of the channels, thus providing low-power dissipation and high-speed capability.
DMOS devices may have either lateral or vertical configurations. A DMOS device having a lateral configuration (referred to herein as an LDMOS), has its source and drain at the surface of the semiconductor wafer. Thus, the current is lateral. Desired characteristics of an LDMOS are a high breakdown voltage, BV, and a low specific on-resistance.
A conventional LDMOS configuration is shown at
10
in
FIG. 1
, with a source region shown at
11
, a drain region at
12
, a gate region at
13
, and a backgate region at
15
. Since the drain region
12
is integral to the NBL
14
, then it cannot be isolated in its own tank from the parasitic collection guardring consisting of NBL
14
and DEEP N+ well
16
. Therefore, when in use as a low side device driving an inductive load, as shown schematically in
FIG. 2
, then when device
10
is switched off or to a condition when the drain
12
of the device
10
consequently becomes negative, the integral parasitic diode D
2
from P-epi
18
/substrate
20
to Deep N+
16
, and the parasitic diode D
1
from the p-type backgate
24
to N-region
22
both conduct. As a consequence of this conduction, the P backgate
24
, P-epi
18
and substrate
20
build up a large amount of minority charge, in this case, electrons. When switched back on, or changed to a blocking state, the electrons either have to be recombined or collected by the drift field set up with an N type region that is positively biased. In the case of
FIG. 1
, the electrons in the P region
24
will have to recombine and will thus create a long recovery time. In the regions
18
and
20
the electrons will get collected by some other N region.
This method of collection can create a very large problem of classical latch-up if collection efficiency is low. Additionally, the extra collection guardring
14
and
16
uses a lot of silicon area and it is desired to eliminate this area usage.
An optimized tank—isolated drain device that overcomes these problems is needed in an advanced CMOS process capable of very high current operating conditions and switching through required breakdown. The improved device should reduce the minority carrier lifetime to improve switching speed. The on resistance performance of this device needs to be extremely competitive to enable the highest current possible at very low drive voltage in the smallest form factor package.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as an array of transistors formed in a p-type layer, and including a second heavily doped p-type region laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region is formed in the p-type layer and proximate a n-type buried layer together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region reduces the minority carrier lifetime proximate the drains of the transistors. The guardring collects the minority carriers and is isolated from the drains of the transistors.
Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N
+
well extending to the buried NBL layer. The guardring is preferably grounded when utilized as the low side transistor to collect minority carriers. A first p-type region is defined proximate the sources of the transistors, and the second p-type region is defined proximate the first p-type region and below the drains to facilitate reducing the minority carrier lifetime thereat. Preferably, the first p-type region is more heavily doped than the second p-type region, and the second p-type region is more heavily doped than the P-epi tank that the transistors are defined within.


REFERENCES:
patent: 5635742 (1997-06-01), Hoshi et al.
patent: 5677205 (1997-10-01), Williams et al.
patent: 6060372 (2000-05-01), Smayling et al.

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