Array of parallel programmable processing engines and...

Details Array of parallel programmable processing engines and... Array of parallel programmable processing engines and...

2008-07-15

2008-07-15

Bullock, Jr., Lewis A. (Department: 2195)

Electrical computers and digital processing systems: virtual mac

Task management or control

Process scheduling

C712S016000, C712S020000, C712S028000, C712S030000, C712S036000

Reexamination Certificate

active

10344020

ABSTRACT:
The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least some threads communicate with each other through communication objects either internally within one processing engine or through the network. A scheduling step of the parallel programmable processing engines is initiated by one or more events, an event being defined by a change of a state variable of a communication object. The array comprises:means for scheduling a scheduling step of the processing engines, the scheduling means comprising means for executing at least a first set of threads in parallel,means for updating state values of communications objects in response to the parallel executing step, andmeans for repeatedly and sequentially scheduling the executing means and the updating means until no more events occur.The present invention also provides a deterministic method of operating such an array.

REFERENCES:
patent: 4414624 (1983-11-01), Summer et al.
patent: 5117490 (1992-05-01), Duxbury et al.
patent: 5241635 (1993-08-01), Papadopoulos et al.
patent: 5524250 (1996-06-01), Chesson et al.
patent: 5655096 (1997-08-01), Branigin
patent: 6154763 (2000-11-01), Thijssen
patent: 7240175 (2007-07-01), Maitland et al.
patent: PCT/US00/00853 (2000-01-01), None
“Multithreaded Systolic/SIMD DSP Array Processor-MUS2DAP”by Sernec, R. et al., 1997 IEEE Workshop on Signal Processing Systems, pp. 448-457, IEEE Publication # XP-002189868, New York, NY, 1997.
“A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler” by Sakurai, R. et al., 1999 Asia and South Pacific Design Automation Conference, pp. 193-196, vol. 1, IEEE Publication # XP 01032328, Piscataway, NJ, no date.

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