Array of non-volatile sonos memory cells

Details Array of non-volatile sonos memory cells Array of non-volatile sonos memory cells

1994-09-30

1995-06-13

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257368, 257401, 257408, 257622, H01L 2906, H01L 2968

Patent

active

054245699

ABSTRACT:
An array of SONOS memory cells includes: a) a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; b) a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; c) a word line commonly interconnecting the adjacent SONOS gates of the pair; and d) separate bit lines separately electrically engaging the separated diffusion regions of the pair. LDD regions are also included. A method of producing such a construction is disclosed.

REFERENCES:
patent: 4714050 (1990-04-01), Shibala
patent: 4975384 (1990-12-01), Boylee
patent: 5234856 (1993-08-01), Gonzalez
patent: 5278438 (1994-01-01), Kim et al.
Kazerounian, R. et al.; Alternate Metal Virtual Ground Eprom Array Implemented In a 0.8 um Process For Very High Denisty Applications, IEDM 91-311, pp. 11.5.1-11.5.4 (1991).
Nozaki et al.; A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application, IEEE Jnl. of Solid State Circuits, vol. 26, No. 4, pp. 497-501, (Apr. 1991).
Chang, Joseph; Nonvolatile Semiconductor Memory Devices, IEEE, vol. 64, No. 7, pp. 1039-1059, (Jul., 1976).

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