Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-05-30
2004-11-23
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C257S773000
Reexamination Certificate
active
06822287
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an array of semiconductor integrated circuit units, and more particularly floating gate memory cells, with strapping lines, to strap row lines with a high voltage applied thereto to reduce the affect of punch through.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
In either floating gate memory cells of the split gate type or stacked gate type, the memory cell has a first region and a second region spaced apart from one another with a channel region therebetween for the conduction of charges. A floating gate stores the charges thereon to control the conduction of charges in the channel region. Finally, a control gate controls the conduction charges in the channel region either directly, in the split gate type, or indirectly, in the stacked gate type.
In the prior art, an array of such non-volatile memory cells are arranged in a plurality of rows and columns with memory cells in the same row having their second region connected together and memory cells in the same column having their first region connected together. In addition, typically, the memory cells in the same row have their control gate connected together. Row decoders and column decoders, which are well known in the art, are also provided to decode addresses and to select a memory cell defined by the intersection of a selected column line and a selected control gate line. Typically, however, in the prior art, either all of the second regions of all the memory cells are connected together, or a plurality of immediately adjacent rows of memory cells have their second regions connected together to define a sector. A sector select line then connects to each of the sectors and appropriate sector address decoders are provided to activate particular sectors. Referring to
FIG. 10A
there is shown a schematic circuit diagram of the prior art in which four sectors are shown with each sector having four rows of memory cells having their second regions connected together. A sector line is connected to each of the four sectors and when a sector line is activated, all of the second region of memory cells in that sector receive a voltage supplied on the sector line.
Referring to
FIG. 10B
, there is shown in greater detail the schematic diagram of an array of non-volatile memory cells of the prior art. Each of the memory cells is of the type shown and disclosed in U.S. Pat. No. 5,029,130, which is of the split gate type having a control gate, first region (designated as bit line BL) and second region (designated a source line V
S5
). As can be seen in
FIG. 10B
, the control gates of each of the rows of memory cells, designated as WL
X
(or word line), are connected singularly and not with each other. Similarly, the column lines which are the bit lines, designated as BL
x
, are connected individually to the first region of the memory cells in the same column and not to one another. However, the source line, designated as V
S5
, which is connected to the second region of the memory cells, are connected together at least for two of the rows of memory cells that are immediately adjacent to one another.
For the memory cell of the type disclosed in U.S. Pat. No. 5,029,130, during programming, a high voltage is supplied to the source line while the bit line has a low voltage supplied thereto. Thus, there creates a high voltage differential between the second region and the first region of the selected memory cell. When a high voltage is supplied to the second region of the selected memory cell and a low voltage is supplied to the first region of the selected cell, a depletion region is formed in the channel region of the selected memory cell. To a first order effect, the selected source line and the selected bit line of the selected memory cell can potentially provide possible punch through between the source line and the bit line. Thus, as shown in
FIG. 10B
, when the memory cell
210
is selected, there is the possibility of punch through effect on memory cell
212
which is in the same column as the selected memory cell and having the same high voltage supplied to its second region due to its source line being connected with the source line of the selected cell
210
.
If the source lines are sufficiently proximate to the depletion regions between adjacent memory cells, the depletion region can merge which can enhance the punch through. This is because the lack of mobile carriers in the merged depletion region which significantly increases the local substrate resistance. In addition, the high voltage sets up a potential barrier between the bit line junction and the substrate. The result of this is that hole current generated near the bit line junction is retarded from draining to the substrate. This is conceptually equivalent to a base resistance in bi-polar devices or a history effect in partially completed silicon-on-isolated devices. Both of these effects are well known to enhance punch through. The impact of this effect further increases if there are significant sources of substrate current, such as that which occurs either inherently or parasitically during certain high voltage erase and programming operations in non-volatile memory devices.
Finally, the possibility of punch increases as the scale of integration increases, i.e., as the size of each non-volatile memory cell decreases.
SUMMARY OF THE INVENTION
Accordingly, in the present invention, a plurality of integrated circuit units are arranged in a plurality of rows and columns where each unit has a first region and a second region spaced apart from one another with a channel region therebetween for the conduction of charges between the first region and the second region. During its operation, a select unit has a voltage applied to its second region. A first plurality of row lines electrically connects the second region of units in the same row. A plurality of column lines electrically connects the first region of units in the same column. Finally, a plurality of strap lines is provided with each strap line electrically connecting a second plurality of row lines not immediately adjacent to one another wherein row lines strapped together by a first strap line are interleaved with row lines strapped together by a second strap line.
REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 5572054 (1996-11-01), Wang et al.
patent: 2003/0223296 (2003-12-01), Hu et al.
Hu Yaw Wen
Lee Dana
Gray Cary Ware & Freidenrich LLP
Prenty Mark V.
Silicon Storage Technology, Inc.
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