Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-03-01
2005-03-01
Booth, Richard A. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06861698
ABSTRACT:
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that are filled with a conducting material such as metal or metalized polysilicon to form blocks of the conducting material that constitute source lines. Each source line extends over and is electrically connected to one of the source regions in each of the active regions.
REFERENCES:
patent: 4757360 (1988-07-01), Farone
patent: 4794565 (1988-12-01), Wu et al.
patent: 4882707 (1989-11-01), Mizutani
patent: 4931847 (1990-06-01), Corda
patent: 4947221 (1990-08-01), Stewart et al.
patent: 5021848 (1991-06-01), Chiu
patent: 5029130 (1991-07-01), Yeh
patent: 5041886 (1991-08-01), Lee
patent: 5101250 (1992-03-01), Arima et al.
patent: 5268319 (1993-12-01), Harari
patent: 5429965 (1995-07-01), Shimoji
patent: 5544103 (1996-08-01), Lambertson
patent: 5572054 (1996-11-01), Wang et al.
patent: 5741719 (1998-04-01), Kim
patent: 5780341 (1998-07-01), Ogura
patent: 5780892 (1998-07-01), Chen
patent: 5783471 (1998-07-01), Chu
patent: 5783473 (1998-07-01), Sung
patent: 5789293 (1998-08-01), Cho et al.
patent: 5796139 (1998-08-01), Fukase
patent: 5808328 (1998-09-01), Nishizawa
patent: 5811853 (1998-09-01), Wang
patent: 5814853 (1998-09-01), Chen
patent: 5994184 (1999-11-01), Fukumoto
patent: 6037228 (2000-03-01), Hsu
patent: 6071802 (2000-06-01), Ban et al.
patent: 6091104 (2000-07-01), Chen
patent: 6103573 (2000-08-01), Harari et al.
patent: 6140182 (2000-10-01), Chen
patent: 6222227 (2001-04-01), Chen
patent: 6255164 (2001-07-01), Liu et al.
patent: 0 389 721 (1990-10-01), None
S. Ogura, A. Hori, J. Kato et al., “Low Voltage, Low Current, High Speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash”, 0-7803-4777, IEEE, Mar. 1998.
C.-P. Chang, H.-H Vuong et al., “SALVO Process for Sub-50 nm Low-VTReplacement Gate CMOS with KrF Lithography”, 0-7803-6441, IEEE, Apr. 2000.
A. Yagishita, S. Tomohiro et al., “Reduction of Threshold Voltage Deviation in Damascene Metal Gate MOSFETs”, 0-7803-5413, IEEE, 3/99.
S. Ogura, A. Hori, J. Kato et al., “Low Voltage, Low Current, High Speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash”, 0-7803-4777, IEEE, Mar. 1998.
C.-P. Chang, H.-H. Vuong et al., “SALVO Process for Sub-50 nm Low-VrReplacement Gate CMOS with KrF Lithography”, 0-7803-6441, IEEE, Mar. 2000.
A Yagishita, S. Tomohiro et al., “Reduction of Threshold Voltage Deviation in Damascene Meta Gate MOSFETs”, 0-7803-5413, IEEE, Mar. 1999.
Booth Richard A.
Gray Cary Ware & Freidenrich LLP
Silicon Storage Technology, Inc.
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