Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-04
2001-06-26
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06253357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an arranging/wiring method of a semiconductor device, and also a semiconductor device arranging/wiring apparatus. More specifically, the present invention is directed to a semiconductor device arranging/wiring method and a semiconductor device arranging/wiring apparatus, suitable for a semiconductor integrated circuit that a so-called “core” is arranged within a semiconductor chip.
2. Description of the Related Art
Conventionally, various layout (involving wiring lines) design methods have been proposed as to semiconductor integrated circuits where cores are arranged in semiconductor chips.
In this specification, a “core” implies a large-scaled functional block capable of realizing a complex operation function by combining basic functional blocks such as an inverter, an AND gate circuit, and an OR gate circuit, used in an ASIC (Application Specified Integrated Circuit). A so-called “core” is designed by a primitive cell combination made of a functional cell and a plurality of functional cells.
As indicated in
FIG. 1
, a core
20
and another core
21
are arranged as a portion of structural elements on an upper surface of a semiconductor chip
19
. A core wiring line
22
and another core wiring line
23
are formed inside the respective core
20
and core
21
.
As previously described, in this semiconductor chip
19
, it is prohibited that a semiconductor chip wiring line
24
passes through regions of these cores
20
and
21
. As a consequence, this chip wiring line
24
passes through a boundary region Rk between these adjoining cores
20
and
21
. The chip wiring lines
24
are collectively arranged in this boundary region Rk.
In this case that both the core
20
and the core
21
are arranged adjacent to each other, as explained before, the interval for separately arranging these cores
20
and
21
must be largely extended in view of the layout design in order that these chip wiring lines
24
may pass through the boundary region Rk under normal arranging condition. As a result, there is a problem that this arranging interval must be extended greater than the area of the semiconductor chip.
It should be noted that this conventional wiring method does not disclose a flow chart for explaining this wiring method.
Next, referring now to
FIG. 2A
to
FIG. 2F
, second related art will be described.
As apparent from these drawings, different from the above-described first related art, in this second related art, it may be allowed that a semiconductor chip wiring line passes through a region of a core.
FIG. 2A
is a flow chart for representing the wiring method of the semiconductor integrated circuit according to this second related art.
FIGS. 2B
,
2
C,
2
D,
2
E and
2
F are schematic chip layout diagrams for showing cores/chips corresponding to the respective wiring steps shown in
FIG. 4A
, and are illustrated at right-sided positions of the respective steps corresponding to the above-described flow chart process of FIG.
4
A.
As apparent from
FIG. 2A
, the layout designing method of this second related art is constituted of a core designing flow step
401
and a chip designing flow step
402
.
Concretely speaking, this core designing flow step
401
contains a core layout step
401
-
1
, and a core operation checking step
401
-
2
.
Also, the chip designing step
402
contains a core arranging step
402
-
1
, a chip layout step
402
-
2
, and a chip operation checking step
402
-
3
.
More specifically,
FIG. 2B
is a schematic diagram for showing a layout state corresponding to the core layout step
401
-
1
.
FIG. 2C
is a schematic diagram for showing a layout state corresponding to the core operation checking step
401
-
2
.
FIG. 2D
is a schematic diagram for indicating a layout state corresponding to the core arranging step
402
-
1
.
FIG. 4D
is a schematic diagram for showing a layout state corresponding to the chip layout step
402
-
2
. Then,
FIG. 2F
is a schematic diagram for indicating a layout state corresponding to the chip operation checking step
402
-
3
.
Referring now to
FIG. 2A
to
FIG. 2F
, the above-explained steps will be explained.
In the core layout designing step
401
-
1
, a layout of a core
25
on a semiconductor chip is firstly designed. Then, in this step
401
-
1
, a core wiring line (pattern)
26
is arranged, and this core wiring line
26
is required to realize the function of this core
25
. Under this state, this core wiring line
26
is present on the core
25
(see schematic layout diagram of FIG.
2
B).
Then, in the core operation checking step
401
-
2
, an operation of the core
25
is checked based upon the wiring load capacitance value of the core wiring line
26
calculated in the core layout step
401
-
1
(see schematic layout diagram of FIG.
2
C).
Next, in the core arranging step
402
-
1
, the layout arrangement of the core
25
, the operation of which has been checked, is carried out with respect to the semiconductor chip
27
(refer to the schematic layout diagram of
FIG. 2D.
)
Next, in the chip layout step
402
-
2
, a chip wiring line
28
required to realize the function of the chip
27
is formed. In this second related art, this chip wiring line
28
may pass through the region of the core
25
. As a consequence, the chip wiring line
28
is formed while passing through the internal region of the core
25
, if required (refer to the schematic layout diagram of FIG.
2
E).
Then, in the chip operation checking step
402
-
3
, the operation of the chip
27
on which the chip wiring line
28
has been formed in the chip layout stage
402
-
2
is carried out (refer to the schematic layout diagram of FIG.
2
F).
Referring now to
FIG. 3
, third related art will be explained.
FIG. 3
schematically shows a layout example of a semiconductor chip
29
in the third related art. In this semiconductor chip
29
, a core
30
and another core
31
are arranged.
In this third related art, both a core wiring line
32
specific to the core
30
and another core wiring line
33
specific to the core
31
are arranged within the respective regions of the core
30
and the core
31
. Within the regions of these cores
30
and
31
, both a channel
35
and another channel
36
are previously formed, through which 3 sets of chip wiring lines
34
formed on the semiconductor chip
29
are branched, and the branched chip wiring lines
34
may pass. It should be understood that there is no flow chart for explaining the wiring method of this third related art similar to the first related art.
The above-described conventional semiconductor integrated circuits and also wiring methods thereof realized by the first to third related art own the following problems:
That is, in the wiring method of the first related art, it is prohibited that the chip wiring line passes through the region of the core on the semiconductor chip. As a consequence when a plurality of cores are arranged on the chip, as indicated in
FIG. 1
, the layout is made by that the chip wiring lines are collectively formed in the boundary region between the cores. In the case that the interval between these cores is narrow, it is practically impossible to arrange these chip wiring lines in this narrow boundary region. To avoid this problem, this narrow interval must be widened and further the chip area must be furthermore enlarged. As a consequence, the entire area occupied by the semiconductor chip would be necessarily increased.
In the second related art, the chip wiring line may pass through the region of the core. However, as represented in
FIG. 2E
, the wiring load capacitance caused by the chip wiring line
28
is added to the core wiring line
26
. Since this wiring load capacitance is added, the signal transfer time within the core wiring line
26
inside the core
25
would be varied. In the core operation checking step
401
-
2
, this operation checking action is carried out without considering the adverse influence caused by the wiring load capacitance by the chip
Hutchins, Wheeler & Dittmar
NEC Corporation
Phan Trong
LandOfFree
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