Arranging address space to access multiple memory banks

Details Arranging address space to access multiple memory banks Arranging address space to access multiple memory banks

2000-01-05

2002-08-06

Verbrugge, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S172000, C711S202000

Reexamination Certificate

active

06430648

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to the field of electronic memory management and more particularly, relates to a method to improve performance of memory subsystems by arranging address space to access multiple memory banks as if it were one contiguous memory.
BACKGROUND OF THE INVENTION
The endeavor for faster and faster computers have reached remarkable milestones since their inception and coming of age during the past sixty years. The beginning of the computer age was characterized by connecting vacuum tubes with large coaxial cables for wiring analog logic. If a new problem was to be solved, the cables were reconfigured. Today, coaxial cables have been replaced with high speed data buses; vacuum tubes have been replaced with high speed logic having transistors of new semiconductor materials and designs, all of which are limited only by the laws of physics.
Initially, the slowest subsystem of computers was the processor subsystem. As processors became more efficient, the limiting function of the computer became the time required to obtain data from sources outside the computer. Once data was moved into the computer, the limitation became the time required for the computer processor to retrieve data stored in memory subsystems external to the processor.
To improve the performance of memory subsystems, memory was brought closer to the processor in the form of cache hierarchies. Cache hierarchies, which are nothing more than limited volume high-speed memories were incorporated into the same integrated circuit as the processor. Thus, data would be immediately available to the processor but the bulk of the data and operating programs was still stored in a larger memory within the computer, referred to as main memory. Efforts were directed toward accessing this main memory subsystem faster and more efficiently. New faster semiconductor materials were developed and used in the RAM—random access memory. More efficient circuits and methods of row and column addressing were developed. The main memory was connected to the processor and other I/O devices through more efficient buses and sophisticated bus command logic. Soon memory control logic became almost as complicated as the logic within the central processing unit having the processor and the cache hierarchy. Memory refresh circuits were developed to maintain the “freshness” and hence the accuracy of the data within main memory. Compression/decompression engines were developed to efficiently rearrange stored data in memory banks.
Still other techniques to improve memory subsystem performance include overlapping and interleaving commands to the memory devices. The amount of data processed with each access to memory was increased to improve memory bus utilization. Interleaving to route commands on different memory buses or different memory cards was improved by providing additional memory in the form of multiple devices or multiple memory banks.
Accessing the multiple memory banks became an art in and of itself. Memory in a computer system may now consist of memory banks of multiple memory cards in which the memory banks can be different sizes, especially when additional memory is added after manufacture of a computer system. One method of accessing memory and keeping track of the address in memory of necessary information is using contiguous memory. Contiguous memory access occurs when after the last byte of one memory bank is accessed, the very first byte of the next memory bank is accessed. When memory is physically maintained contiguously, however, address generation for multiple memory banks of various sizes is complicated and adds timing delays because the hardware that generates the address to the memory banks must subtract all other memory bank sizes preceding the memory bank that is currently being accessed. Memory bank address generation is greatly simplified when the view of physical memory is non-contiguous, i.e., the address space within the memory banks are broken into non-contiguous sections.
There remains a need to simplify access to memory subsystems without additional cost and additional hardware to maintain a complex address space in memory while still maintaining high bandwidth and high data bus utilization.
SUMMARY OF THE INVENTION
These needs and others that will become apparent to one skilled in the art are satisfied by a method to arrange addresses in a memory system, comprising the steps of: storing the total size of a plurality of contiguous memory banks and storing the size of each of said memory banks; selecting one of the memory banks by reading the highest order bits above the bits representative of the size of the smallest memory bank; and determining an offset position of an address in the selected memory bank from the physical beginning of the selected memory bank by summing the bits of lower order than the bit representing the size of the selected memory bank.
If the highest order bits above the bit representative of the size of the smallest memory bank are zero, then the address is placed in the first memory bank. Quite simply, the memory bank selected is the one whose low address is less than or equal to the highest order bits and whose high address is greater than the highest order bits.
The invention may also be considered a computer system, comprising a computer processor, a memory connected on a bus to the processor; the memory comprising a memory controller connected on a memory bus to a plurality of contiguous memory banks, each having a low address, a high address, and a physical beginning. The memory controller has a plurality of registers which store the size of each memory bank in which the registers are used by bank select logic and address generation logic. The computer system also has a plurality of bus units connected to the processor and/or the memory via an external bus and the processor and or one of the bus units to request access to an address in said memory wherein the requested address is decoded by the bank select logic which reads the address bits that are of higher order than the size of the smallest memory bank and selects the memory bank whose low address is less than or equal to the requested address and whose high address is greater than the requested address; and wherein the address generation logic generates a position in the selected memory bank by summing the address bits of lower significance than the size of the selected bank and offsetting the sum from the physical beginning of the selected bank.
Another aspect of the invention is a memory system apparatus for the storage of and retrieval of binary data, comprising a means to read a requested binary address to access the memory system having a plurality of memory banks, each bank having a low address not necessarily coincident with the physical beginning of the memory bank and a high address; means to decode the bits of the binary address that are of higher order than the smallest of the memory banks in the memory system; means to select the memory banks whose low address is less than or equal to the higher order bits and whose high address is greater than the higher order bits; means to decode the bits of the binary address that are lower order than the bits representing the size of the selected memory bank; means to offset the requested binary address from the physical beginning of the selected memory bank by summing the bits of lower order; and means to store data to or retrieve data from the offset in the selected memory bank.
Further scope of applicability of the present invention will become apparent from the detailed description given herein. It should be understood, however, that the detailed description and the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only. Various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art upon review of the detailed description.


REFERENCES:
patent: 5012408 (1991-04-01), Conroy
patent: 5392252 (1995-02-01), Rimpo et al.
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