Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2000-07-12
2002-03-26
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S063000, C365S194000, C365S230030, C365S233100, C365S221000, C365S220000
Reexamination Certificate
active
06362995
ABSTRACT:
FIELD OF THE INVENTION
the present invention relates to integrated circuit memory devices, and more particularly to arrangements of functional blocks in integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Integrated circuit devices such as integrated circuit memory devices are widely used in consumer and commercial applications. Integrated circuit memory devices continue to increase in integration density and speed, while allowing reduced power consumption. For example, synchronous Dynamic Random Access Memories (DRAMs) that can operate in synchronization with system clocks have been developed to allow high speed operation. Dual Data Rate (DDR) synchronous DRAMs also have been developed to allow high performance memory devices.
Electronic systems such as data processing systems often use buses including a plurality of signal lines to interconnect integrated circuit devices, so that the integrated circuit devices can communicate with one another. Output drivers are generally included in microprocessor logic and/or memory intergrated circuits in order to drive signals that are internally generated in the integrated circuit onto the bus. These output drivers are generally driven by voltage level signals.
Recently, however, in order to achieve high speed operations and/or other advantages integrated circuit devices that include current mode output drivers have been provided. The use of current mode output drivers can reduce the peak switching current and signal reflections on the bus, to thereby allow low power, high performance communications between integrated circuits.
One technology that uses current mode output drivers is the Rambus technology that is marketed by Rambus Inc., Mountain View, Calif. The Rambus technology is described in U.S. Pat. No. 5,473,575 to Farmwald et al., U.S. Pat. No. 5,578,940 to Dillon et al., U.S. Pat. No. 5,606,717 to Farmwald et al. and U.S. Pat. No. 5,663,661 to Dillon et al. Also see U.S. Pat. No. 6,072,747 to Yoon that is assigned to the assignee of the present invention. Integrated circuit devices that include current mode output drivers also will be referred to herein as Rambus devices.
Rambus devices may operate at high data rates, for example at data rates of up to 800 MHz or more. Moreover, large amounts of data may be simultaneously read from memory cell arrays in Rambus DRAMS, so that large amounts of power may be consumed.
The area of the integrated circuit substrate, the operating speed and/or the power consumption may be considered when designing a Rambus device. Since the area of the substrate, the operating speed and the power consumption may depend on the arrangement of the functional blocks thereof, the functional blocks should be arranged such that the area can be reduced or minimized, the operating speed can be increased or maximized, and/or the power consumption can be reduced or minimized. An arrangement of functional blocks in a Rambus Dynamic Random Access Memory (DRAM) is disclosed in U.S. application Ser. No. 09/280,026 to Yoo, filed Mar. 26, 1999, now U.S. Pat. No. 6,151,264, entitled Integrated Circuit Memory Devices Including a single Data Shift Block Between First and Second Memory Banks, assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference in its entirety. Another arrangement of functional blocks for a Rambus device is disclosed in U.S. application Ser. No. 09/466,536 to Moon, filed Dec. 17, 1999, now U.S. Pat. No. 6,256,218, entitled “Integrated Circuit Memory Devices Having Adjacent Input/Output Buffers and Shift Blocks”, assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference in its entirety.
FIG. 1
is a block diagram showing the arrangement of functional blocks in a Rambus DRAM disclosed in the above-cited application Ser. No. 09/280,026. Referring to
FIG. 1
, the disclosed Rambus DRAM includes first and second memory banks
111
and
121
, first and second core interfaces
113
and
123
, first and second data shift blocks
131
and
141
, all interface logic block
151
, first and second input/output units
161
and
162
, a delay locked loop circuit
163
and a pad block
171
in an integrated circuit substrate
101
such as a semiconductor substrate. In a Rambus DRAM of
FIG. 1
, the first data shift block
131
, the interface logic block
151
, an input/output block including, the first input/output unit
161
, the delay locked loop circuit
163
and the second input/output unit
162
the pad block
171
and the second data shift block
141
are sequentially arranged between the first memory bank
111
and the second memory bank
121
.
This Rambus DRAM may have a disadvantage in that the area of a substrate
101
may increase because the first data shift block
131
for the first memory bank
111
and the second data shift block
141
for the second memory bank
121
are separate blocks. Moreover, since the first and second data shift blocks
131
and
141
are remote from the delay locked loop circuit
163
which generates internal clock signals including an input control clock signal SCLK and an output control clock signal TCLK, the lengths of clock lines for transmitting the input control clock signal SCLK and the output control clock signal TCLK to the first and second data shift blocks
131
and
141
may increase. This may increase the load on the outputs of the delay locked loop circuit
163
and may increase power consumption.
Furthermore, since the first data shift block
131
is remote from the pad block
171
, the length of a wire or conductor for supplying a power supply voltage from the pad block
171
to the first data shift block
131
may increase. This may cause noise to occur in the power supply voltage and/or a ground voltage which are supplied from the pad block
171
to the first data shift block
131
, so that the operation of the Rambus DRAM may become unstable.
FIG. 2
is a block diagram showing an arrangement of functional blocks in another Rambus DRAM disclosed in the above-cited application Ser. No. 09/280,026.
Referring to
FIG. 2
, a Rambus DRAM comprises first and second memory banks
211
and
221
, first and second core interfaces
213
and
223
, an interface logic block
231
, first and second input/output units
241
and
242
, a delay locked loop circuit
243
, a pad block
251
and a data shift block
261
in an integrated circuit substrate
201
such as a semiconductor substrate. In the Rambus DRAM, the interface logic block
231
, an input/output block including the first input/output unit
241
, the delay locked loop circuit
243
, and the second input/output unit
242
, the pad block
251
and the data shift block
261
are sequentially arranged between the first memory bank
211
and the second memory bank
221
. Moreover, in this Rambus DRAM, a data shift block for the first memory bank
211
and a data shift block for the second memory bank
221
are integrated into the single data shift block
261
. Consequently, the area of the substrate
201
of
FIG. 2
may decrease compared with that in the Rambus DRAM of FIG.
1
.
Furthermore, since there is one data shift block, the lengths of clock lines connected to an output of the delay locked loop circuit
243
, for transmitting the input control clock signal SCLK and the output control clock signal TCLK, may be shorter than in the Rambus DRAM shown in FIG.
1
. Accordingly, the load on the output of the delay locked loop circuit
243
may decrease so that power consumption may be reduced as compared with the Rambus DRAM shown in FIG.
1
. In addition, since the data shift block
261
is adjacent to the pad block
251
, a wire or conductor for transmitting the power supply voltage and the ground voltage from the pad block
251
to the data shift block
261
may be shorter. Consequently, noise occurring in the power supply voltage and the ground voltage may be reduced.
However, since the Rambus DRAM shown in
FIG. 2
may be designed such that data lines L
2
and L
4
for transmit
Hwang Hong-sun
Moon Byung-mo
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Tran Andrew Q.
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