Arrangements for developing integrated circuit designs

Details Arrangements for developing integrated circuit designs Arrangements for developing integrated circuit designs

2007-11-05

2010-12-14

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07853912

ABSTRACT:
In some embodiments, a method is disclosed for converging on an acceptable integrated circuit design for an integrated circuit. The method can include selecting a path, determining if the path has a timing deficiency, segmenting the path into path segments and allocating the timing deficiency across the segments according to attributes of the path segments. Segments can have attributes such as a design freeze when the design is mature or “optimum.” Allocating can include allocating the timing deficiency across path segments according to attributes such as the proportion of the length of a segmented path to the overall path length. Allocating can include allocating the timing deficiency to path segments based on attributes provided as user input.

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