Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2000-08-17
2004-05-18
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S112000, C712S010000, C709S201000, C711S147000
Reexamination Certificate
active
06738840
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a data processing arrangement comprising a plurality of processors and a memory interface via which the processors can access a collective memory. The invention may be applied in, for example, an integrated circuit device capable of decoding an MPEG data stream.
DESCRIPTION OF THE PRIOR ART
Patent Specification U.S. Pat. No. 5,072,420 describes an interface via which a plurality of peripheral and external devices can access a DRAM memory (Dynamic Random Access Memory). The interface has an input and output channel for each peripheral and external device. Each channel includes a FIFO memory (First In, First Out) which connects the relevant device to the DRAM memory.
SUMMARY OF THE INVENTION
It is an object of the invention is to enable implementations to be realized at comparatively low cost, particularly implementations in the form of integrated circuits.
The invention takes into account the following aspects. A memory generally comprises elements forming memory cells and additional elements for accessing the memory cells. When the memory is small, the additional elements are proportionally large. Therefore, one might say that a comparatively small memory has a low efficiency. For example, let us consider a memory which forms part of an integrated circuit. If the memory is comparatively small, it has only a relatively small storage capacity per unit of surface area. In other words, the memory occupies a comparatively large surface area in relation to the amount of data it can store.
In the prior art, the interface between the DRAM memory and the peripheral and external devices comprises a FIFO memory for each device. When it is assumed that this interface is realized in the form of an integrated circuit, the FIFO memories occupy a comparatively large surface area. Moreover, each FIFO memory requires specific connections such as, for example, power supply rails. This complicates the routing of the connections. Thus, the prior-art interface occupies a comparatively large surface area and is comparatively difficult to implement.
According to the invention, an arrangement of the type defined in the opening paragraph comprises:
an interface memory for temporarily storing data belonging to different processors;
a control circuit for controlling the interface memory in such a manner that it forms a FIFO memory for each of the different processors.
Thus, the interface memory in fact replaces an arrangement of separate FIFO memories as used in the prior art. The control circuit can be comparatively simple as compared with all the additional elements that are comprised in an arrangement of separate FIFO memories. The invention consequently enables the desired storage capacity to be realized with a smaller number of elements than in the prior art. More specifically, the invention enables a memory interface to be implemented on a comparatively small surface area of an integrated circuit. As a result of this, the invention enables implementations at comparatively low cost.
The invention and additional features, which can be used advantageously for putting the invention into effect, will be described in greater detail hereinafter with reference to the drawings.
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De Perthuis Hugues
Mutz Stéphane
Nouvet Thierry
Koninklijke Philips Electronics , N.V.
Mai Rijue
Perveen Rehana
Ure Michael J.
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