Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1999-06-11
2000-11-14
Elms, Richard
Static information storage and retrieval
Addressing
Plural blocks or banks
365 63, 365233, G11C 800
Patent
active
061479241
ABSTRACT:
There is provided a semiconductor memory device which includes a plurality of memory cell blocks arranged in rows and columns. Each memory cell block includes a plurality of memory cells for storing data. A plurality of data input/output circuits are divided into a first group and a second group. The first group and the second group are associated with and disposed between a respective subset of the memory cell blocks. The data input/output circuits have a plurality of data input/output pins. A plurality of address signal circuits are arranged between the first group and the second group for receiving externally applied address signals. The semiconductor memory device is packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the data input/output circuits of the first and second groups are collectively arranged adjacent to each other.
REFERENCES:
patent: 5517442 (1996-05-01), Kirihata et al.
patent: 5604710 (1997-02-01), Tomishima et al.
patent: 5627792 (1997-05-01), Tsujimoto
patent: 5930198 (1999-07-01), Ryan
patent: 5995404 (1999-11-01), Nakaumura et al.
Jeon Jun-Young
Lee Chang-Ho
Elms Richard
Nguyen Hien
Samsung Electronics Co,. Ltd.
LandOfFree
Arrangement of data input/output circuits for use in a semicondu does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arrangement of data input/output circuits for use in a semicondu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement of data input/output circuits for use in a semicondu will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2071705