Arrangement in a power mosfet

Details Arrangement in a power mosfet Arrangement in a power mosfet

2001-07-18

2004-11-16

Wilczewski, Mary (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S335000, C257S336000

Reexamination Certificate

active

06818951

ABSTRACT:

TECHNICAL FIELD
The invention relates to power MOS transistors and more specifically to an arrangement for improving linearity and efficiency of such transistors.
BACKGROUND OF THE INVENTION
A power MOS transistor consists of an intrinsic structure that repeats itself over and over again. Thus, a power MOS transistor can be seen as a plurality of small transistor segments connected in parallel.
The power MOS transistor operates with its source terminal connected to ground and its drain terminal connected to a positive supply voltage.
When a positive voltage on its gate terminal exceeds a threshold voltage of the transistor, an n-type inversion region will form underneath its gate, allowing for current to pass between its drain and source.
Traditionally, the threshold voltage is desired to be uniform throughout the transistor so that current sharing is equal between the transistor segments and maximum efficiency is obtained when the transistor is operating at full power. This is to say that all transistor segments shall have the same threshold voltage.
In e.g. a power LDMOS transistor operating in class AB, a gate DC bias voltage slightly above the threshold voltage will cause a quiescent drain current to flow through the transistor.
The quiescent drain current is a relatively small contributor to the total drain current consumption at full output power, typically around 10%, and thus has little impact on overall efficiency.
At low levels of output power (so called backed-off conditions), this is no longer true. Here, the quiescent drain current is a significant, or even the dominant, contributor to total drain current consumption.
In an LDMOS transistor, linearity will improve significantly as output power is decreased, which is why the backed-off mode of operation is of particular interest.
Linearity performance is also a strong function of gate DC bias.
There exists an optimal quiescent drain current value that results in best linearity performance at a given output power level. To lower the quiescent drain current further in order to improve efficiency will degrade the linearity.
SUMMARY OF THE INVENTION
The object of the invention is to improve efficiency and linearity in a power MOS transistor under backed-off operating conditions with maintained peak power capability.
This is attained in accordance with the invention in that at least one group of said transistor segments has another threshold voltage than the rest of the transistor segments.
Thus, the threshold voltage is graded throughout the transistor.
Hereby, more and more of the transistor, i.e. actually more and more transistor segments, will become active as the input voltage on its gate terminal is increased, allowing for improved efficiency and/or linearity under backed-off operating conditions with maintained peak power capability.


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