Arrangement for verifying that memory external to a network...

Details Arrangement for verifying that memory external to a network... Arrangement for verifying that memory external to a network...

2006-04-04

2006-04-04

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07024603

ABSTRACT:
A method and arrangement is provided for testing memory external to a network switch and a memory interface bus connecting the external memory to the network switch. The method includes writing, via the memory interface bus and on a per-bit basis, a first prescribed logic pattern to a prescribed region of the memory to check for one of a bus short to ground and a short between adjacent pins of the memory. The first prescribed logic pattern is read to verify operation of the prescribed region of the memory. The method includes writing, via the memory interface bus and on a per-bit basis, a second prescribed logic pattern, complementary to the first prescribed logic pattern, to a prescribed region of the memory to check for one of a bus short to power and a short between adjacent pins of the memory. The second prescribed logic pattern is read to verify operation of the prescribed region of the memory.

REFERENCES:
patent: 3784910 (1974-01-01), Sylvan
patent: 5953335 (1999-09-01), Erimli et al.
patent: 6295620 (2001-09-01), Togo

Affiliated with

Also associated with

Rating

Arrangement for verifying that memory external to a network... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Arrangement for verifying that memory external to a network..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement for verifying that memory external to a network... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3577797