Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
Reexamination Certificate
2001-01-29
2004-01-13
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Transmission facility testing
C714S719000, C714S735000, C714S742000, C714S750000
Reexamination Certificate
active
06678845
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to testing of integrated network devices such as integrated network switches configured for switching data packets between subnetworks.
2. Background Art
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interface devices at each network node to access the network medium.
Switched local area networks are encountering increasing demands for higher speed connectivity, more flexible switching performance, and the ability to accommodate more complex network architectures. For example, commonly-assigned U.S. Pat. No. 5,953,335 discloses a network switch configured for switching layer
2
type Ethernet (IEEE 802.3) data packets between different network nodes; a received layer
2
type data packet may include a VLAN (virtual LAN) tagged frame according to IEEE 802.1p (802.1D) protocol that enables the network switch to perform more advanced switching operations. For example, the VLAN tag may specify another subnetwork (via a router) or a prescribed group of stations.
A network switch may be tested using a network evaluation board, such as the commercially available Net 186 Embedded Ethernet Demonstration Board, to program the port registers of the high-performance integrated network switch under test. After programming the port registers, a test engineer will perform prescribed tests. However, improper programming of the port registers due to, for example, signal integrity issues may cause the network switch under test to fail the prescribed test. Hence, a test engineer may start a trial and error process to determine the cause of the failure. For example, non-operating switches might be re-soldered to the test board, the physical layer devices (PHYs) might be replaced, etc., in an effort to locate the problem and cause the switch to function properly. In may cases, after spending significant time yet failing to locate the source of the failure, the switch may be simply discarded based on the mistaken belief that the switch is defective.
SUMMARY OF THE INVENTION
There is a need for an arrangement for testing programmed port registers of an integrated network device by reading back the programmed value to ensure that the port register was programmed properly.
This and other needs are attained by the present invention where a method of testing a port register of an integrated network includes establishing a programmable value for a register of an integrated network device. The register is programmed with a prescribed value configured to represent the programmable value. A read value is read from the register following the programming with the prescribed value. The programming step is validated by comparing the read value with the programmable value.
Another aspect of the present invention provides an apparatus configured for testing a register of an integrated network device. The system includes an integrated network device having a port register. Controller structure is connected to the integrated network switch and is configured to program the register with a prescribed value configured to represent a programmable value, to read back from the register a read value following programming with the prescribed value, and to validate the programming step by comparing the read value with the programmable value.
Hence, testing a port register by reading back the programmed value and comparing the value against the intended programmed value saves much time troubleshooting non-operating network switches which fail due to port register programming problems.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.
REFERENCES:
patent: 5953335 (1999-09-01), Erimli et al.
patent: 6501690 (2002-12-01), Satoh
patent: 6546482 (2003-04-01), Magro et al.
patent: 6550023 (2003-04-01), Brauch et al.
patent: 6553486 (2003-04-01), Ansari
patent: 6564161 (2003-05-01), Lin et al.
Advanced Micro Devices , Inc.
Dildine R. Stephen
Manelli Denison & Selter PLLC
Turkevich Leon R.
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