Arrangement for solder bump formation on wafers

Details Arrangement for solder bump formation on wafers Arrangement for solder bump formation on wafers

2011-07-19

2011-07-19

Sandvik, Benjamin P (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Solder wettable contact, lead, or bond

C257S780000, C257SE23023, C257SE21508, C257SE21515, C438S611000, C438S612000, C228S254000, C228S256000, C228S111500

Reexamination Certificate

active

07982320

ABSTRACT:
An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.

REFERENCES:
patent: 6056191 (2000-05-01), Brouillette et al.
patent: 6123248 (2000-09-01), Tadauchi et al.
patent: 6609652 (2003-08-01), MacKay et al.

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