Arrangement comprising a memory device and a...

Details Arrangement comprising a memory device and a... Arrangement comprising a memory device and a...

2006-09-12

2006-09-12

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C713S500000, C326S093000

Reexamination Certificate

active

07106654

ABSTRACT:
An arrangement comprises a memory device for storing data, and a program-controlled unit with a memory interface for reading data out of the memory device. The memory device is supplied with a first clock signal and transmits the data at the rate of a second clock signal, and the second clock signal to the memory interface when the memory interface performs a read access. The first clock signal is also supplied to the memory interface which generates from this signal a third clock signal which has the same frequency as the first and second clock signal but a predetermined phase shift with respect to the second clock signal. The memory interface accepts the data with the rising and/or falling edges of the third clock signal or the inverted third clock signal, and the third clock signal is also used as clock signal by other components of the memory interface.

REFERENCES:
patent: 5805873 (1998-09-01), Roy
patent: 6198688 (2001-03-01), Choi
patent: 6760857 (2004-07-01), Lau et al.
patent: 6778465 (2004-08-01), Shin
patent: 6791889 (2004-09-01), Peterson

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