Radiant energy – Inspection of solids or liquids by charged particles – Electron probe type
Reexamination Certificate
1999-07-22
2002-09-17
Nguyen, Kiet T. (Department: 2881)
Radiant energy
Inspection of solids or liquids by charged particles
Electron probe type
Reexamination Certificate
active
06452176
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor device assemblies, and more particularly to techniques for analyzing substrate associated with an integrated circuit.
BACKGROUND OF THE INVENTION
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality has been an increase in the number and complexity of the manufacturing processes.
As the manufacturing processes for semiconductor devices increase in difficulty, methods for analyzing the devices become increasingly important. A particular attribute of semiconductor devices that requires testing is the integrity of the device substrate, such as the substrate morphology, elemental or chemical composition, and crystallographic structure. During manufacture and processing, the crystalline structure of semiconductor device substrate often becomes damaged. When materials are implanted in the device during operations such as ion implantation, the ions strike the device substrate and lose their energy via electronic and nuclear collisions. If the transferred energy during a nuclear collision is high enough, the atoms are displaced from their lattice sites in the crystalline structure, damaging the substrate. The magnitude of the damage increases as the energy transferred during a collision increases. Damage can also occur during post-processing circuit usage; such damage includes, for example, CMOS latch-up events.
Damaged substrate results in reduced mobility in the damaged regions and defect levels in the band gap of the material, including deep-level traps for both electrons and holes, which have a tendency to capture free carriers from the conduction and valence bands. In addition to damaged crystalline structure, other abnormalities in the semiconductor devices may exist, for example, in the form of impurities in the substrate. If not repaired, the damaged regions may exhibit problems such as high resistivity.
As the semiconductor industry continues to demand increasingly complex and numerous manufacturing processes, the tendency for defects to occur within the substrate increases. Therefore, it would be helpful to have the ability to efficiently test structure within the semiconductor substrate to detect substrate damage.
SUMMARY OF THE INVENTION
The method and apparatus described herein involves determining a degree of substrate damage in an integrated circuit die. In an example embodiment, the back side of an integrated circuit die is thinned, and an examination region is exposed. The examination region is scanned with an electron beam, and backscattered electrons are detected in response. The detected backscattered electrons are used and an electron channeling pattern for the scanned region is provided. The electron channeling pattern is examined, and a degree of substrate damage is detected therefrom.
In another example embodiment, a system is configured and arranged to detect a degree of substrate damage in an integrated circuit die. A beam generator is constructed and arranged to thin the back side of the die and expose a region for examination. An electron beam scanner is constructed and arranged to scan the region with an electron beam and, in response, to detect backscattered electrons. The detected backscattered electrons are used by a processor configured and arranged to provide an electron channeling pattern for the scanned region. A computer arrangement is programmed to examine the electron channeling pattern and determine therefrom a degree of substrate damage.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 5191213 (1993-03-01), Ahmed et al.
patent: 5424254 (1995-06-01), Damiot
patent: 5525806 (1996-06-01), Iwasaki et al.
patent: 5698474 (1997-12-01), Hurley
patent: 5700697 (1997-12-01), Dlugokecki
patent: 5821549 (1998-10-01), Talbot et al.
patent: 5930588 (1999-07-01), Paniccia
patent: 5963781 (1999-10-01), Winer
patent: 5972725 (1999-10-01), Wollesen et al.
patent: 6093331 (2000-07-01), Wollesen
patent: 6281025 (2001-08-01), Ring et al.
Joy, D.C., “SEM Microcharacterization of Semiconductors”, Dec. 11, 1990, pp. 71-72, 75, 81, 83, 93, 100, 112-114.
“Phase ID-Microphase Identification for SEMs”, Noran Instruments, 1998, pp. 1-4.
LandOfFree
Arrangement and method for using electron channeling... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arrangement and method for using electron channeling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement and method for using electron channeling... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2894364