Arrangement and method for update of configuration cache data

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S113000, C711S154000, C711S147000

Reexamination Certificate

active

10600549

ABSTRACT:
An arrangement and method for update of configuration cache data in a disk storage subsystem in which a cache memory (110) is updated using two-phase (220, 250) commit technique.This provides the advantage that known changes to the subsystem do not require an invalidate/rebuild style operation on the cache. This is especially important where a change will invalidate the entire cache.

REFERENCES:
patent: 5895493 (1999-04-01), Gatica
patent: 6321298 (2001-11-01), Hubis
patent: 6330642 (2001-12-01), Carteau
patent: 6584546 (2003-06-01), Kavipurapu
patent: 6601138 (2003-07-01), Otterness et al.
patent: 2001/0049774 (2001-12-01), Otterness et al.
Tanenbaum, “Structured Computer Organization”, © 1984, Prentice-Hall, Inc., p. 10-12.

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