Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-06-26
2007-06-26
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S113000, C711S154000, C711S147000
Reexamination Certificate
active
10600549
ABSTRACT:
An arrangement and method for update of configuration cache data in a disk storage subsystem in which a cache memory (110) is updated using two-phase (220, 250) commit technique.This provides the advantage that known changes to the subsystem do not require an invalidate/rebuild style operation on the cache. This is especially important where a change will invalidate the entire cache.
REFERENCES:
patent: 5895493 (1999-04-01), Gatica
patent: 6321298 (2001-11-01), Hubis
patent: 6330642 (2001-12-01), Carteau
patent: 6584546 (2003-06-01), Kavipurapu
patent: 6601138 (2003-07-01), Otterness et al.
patent: 2001/0049774 (2001-12-01), Otterness et al.
Tanenbaum, “Structured Computer Organization”, © 1984, Prentice-Hall, Inc., p. 10-12.
Carr David John
Jones Michael John
Key Andrew
Nicholson Robert Bruce
Scales William James
Harrington & Smith ,LLP
International Business Machines - Corporation
Peugh Brian R.
LandOfFree
Arrangement and method for update of configuration cache data does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arrangement and method for update of configuration cache data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement and method for update of configuration cache data will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3864117