Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Patent
1996-11-20
1999-10-12
Rinehart, Mark H.
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
709248, 710 16, G06F 104, G06F 1516
Patent
active
059648830
ABSTRACT:
An arrangement for monitoring clock frequency variations on a peripheral bus is provided to improve operations of the peripheral device despite changes in the clock frequency. In one aspect of the arrangement, a processing unit is coupled to a host bus which in turn is coupled to a peripheral bus which is coupled to a peripheral device. A monitoring arrangement is provided which detects a change in the clock frequency of the peripheral bus and determines if the frequency change exceeds a threshold associated with the peripheral device. If the threshold is exceeded, the peripheral device is informed that the clock frequency of the peripheral bus has changed. A peripheral device operating a different operating levels may use the information from the monitoring arrangement to alter the operating level of the peripheral device to conform to the new bus clock frequency.
REFERENCES:
patent: 4344132 (1982-08-01), Dixon et al.
patent: 5115503 (1992-05-01), Burkin
patent: 5566325 (1996-10-01), Bruce, II et al.
patent: 5657482 (1997-08-01), Klein
patent: 5687371 (1997-11-01), Lee et al.
Microsoft Press Computer Dictionary, pp. 76, 196 (2d ed.), 1994.
Advanced Micro Devices
Rinehart Mark H.
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