Arrangement and method for efficient calculation of memory addre

Details Arrangement and method for efficient calculation of memory addre Arrangement and method for efficient calculation of memory addre

1996-05-10

1999-01-12

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Dynamic-type storage device

711114, 711202, 711209, 711221, 395653, 395681, G06F 1206

Patent

active

058600795

ABSTRACT:
A block storage memory management scheme. According to the disclosed embodiments, a memory list of data is generated from a set of address ranges, a descriptor is created to interact with the memory list, and data is retrieved by preparing the memory specified by the descriptor for an input/output operation, performing the operation, and deleting the descriptor. Memory mappings are delayed as long as possible to enhance the performance of the system, particularly for RAID applications.

REFERENCES:
patent: 4928237 (1990-05-01), Bealkowski et al.
patent: 5555387 (1996-09-01), Branstad et al.
patent: 5689678 (1997-11-01), Stallmo et al.
"The Raid Primer" (1994) published by the RAID Advisory Board, Inc., St. Peter, Minnesota.

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