Arrangement and method for allowing sequence-independent command

Details Arrangement and method for allowing sequence-independent command Arrangement and method for allowing sequence-independent command

1996-09-26

2000-04-25

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710100, 710112, 711145, 712204, 714 50, G06F 1338

Patent

active

06055598&

ABSTRACT:
An arrangement for providing command responses in a sequence that is independent of the sequence that commands are initiated by an initiating bus to a target bus. A first memory array stores commands from the initiating bus in a first sequence, and provides the commands to the target bus in a first sequence. Multiple delayed completion registers are provided, each to receive and store one of the commands entered into the first memory array. The delayed completion registers re-enter its corresponding stored command into the first memory array when a request is received to reissue the command. A second memory array stores command responses in a second sequence that relates to the order that their corresponding commands were successfully completed on the target bus.

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"DECchip 21052 PCI-to-PCI Bridge Data Sheet", Digital Equipment Corporation, Order No.: EC-QHURA-TE, Jun. 1995, pp. (i)-A2.

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