Arithmetic unit with reduced startup time and method of...

Details Arithmetic unit with reduced startup time and method of... Arithmetic unit with reduced startup time and method of...

2006-09-12

2006-09-12

Peikari, B. James (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S117000, C711S118000, C708S490000, C709S239000, C710S038000

Reexamination Certificate

active

07107407

ABSTRACT:
An arithmetic unit includes a switching device16and a cache controller19.The switching device16determines whether desired data to be read by the CPU11is in a RAM14,and allows, depending on a result of the determination, the CPU11to directly read the desired data from a ROM13.The cache controller19controls a cache12so that the RAM14is initialized based on cache data corresponding to the desired data stored in the cache12.In an arithmetic unit having a CPU, a cache, RAM, and ROM configured in the above manner, the time required for a startup process is reduced.

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“Method of Testing Personal Computer Using a Static Random Access Memory”. IBM Technical Disclosure Bulletin, IBM Corp., New York. vol. 37, No. 7, Jul. 1994, pp. 107-108.

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