Arithmetic unit and data processing unit

Details Arithmetic unit and data processing unit Arithmetic unit and data processing unit

1998-11-30

2001-12-18

Ngo, Chuong Dinh (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C341S063000, C341S067000

Reexamination Certificate

active

06332152

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an arithmetic unit and a data processing unit mounted in a digital signal processor and the like.
2. Description of the Prior Art
A prior art data processing unit for performing data comparison will be described below. The prior art data processing unit hereinafter described is primarily used as a special-purpose circuit when performing variable length encoding of image information, etc. after a discrete cosine transform. The prior art data processing unit has the circuitry shown, for example, in
FIG. 16
, in which reference character
1
x
is a memory (8-bit-data memory with addresses
0
to
63
),
2
x
is a read control circuit,
3
x
is a zero run counter,
4
x
is a zero decoder,
5
x
is memory data,
6
x
is a memory read control signal,
7
x
is an enable signal,
8
x
is a zero decode signal, and
9
x
is a zero run count signal. Further, reference character
10
x
is a variable length encoder for performing variable length encoding.
Operation of the thus configured data processing unit will be described below with reference to the waveform diagram of
FIG. 17
(reference characters shown correspond to those in FIG.
16
). In
FIG. 17
, a typical memory readout address signal is depicted as the memory readout control signal
6
x.
Waveform
1
w
in
FIG. 17
is used as the operating clock (CLK) of the data processing unit of FIG.
16
. The read control circuit
2
x
in
FIG. 16
reads out the memory data
5
x
at the address specified by the memory readout control signal
6
x
when the enable signal
7
x
is at a high level (hereinafter referred to as H level) (in the illustrated example, addresses are generated in the order of
0
,
1
,
2
, . . . ,
63
).
The zero decoder
4
x
decodes the memory data
5
x
and, when the memory data shows a value 0, sets the zero decode signal
8
x
to the H level. At this time, the zero run counter
3
x
counts up, thus counting the number of
0
s
occurring consecutively. When the zero decode signal
8
x
is at a Low level (hereinafter referred to as the L level), the zero run counter
3
x
shows a value 0.
The thus generated zero run count signal
9
x
and the zero decode signal
8
x
are output together with the memory data
5
x
; the variable length encoder circuit
10
x
at the following stage performs data processing using the zero run count signal
9
x
and memory data
5
x
at the time that the zero decode signal
8
x
is at the L level. Variable length encoding is a process in which data is compressed by treating the number of consecutive data zeros and the nonzero data following the data zeros as one set of data. Strictly speaking, quantization is performed before the variable length encoding. In the illustrated example, the zero run count signal
9
x
indicates the number of consecutive data zeros and the memory data
5
x
the nonzero data.
Since specialized circuitry, such as the zero run counter
3
x
and the zero decoder
4
x
, is used to sequentially detect and output the number of consecutive zeros and the nonzero data following the data zeros, the prior art data processing unit lacks versatility and cannot, for example, detect the number of consecutive data values other than zeros; further, when, for example, it becomes necessary to perform an addition or comparison in addition to sequentially detecting and outputting the number of consecutive data zeros and the nonzero data following the data zeros, extra circuitry for performing the addition or comparison has to be added.
Furthermore, the prior art data processing unit, when mounted as a special-purpose circuit in a digital signal processor or the like, is not able to continuously perform the data processing using the zero run count signal
9
x
and-memory data
5
x
if zeros continue to appear in the memory data. The reason is that, since data compression is performed using both the number of consecutive zeros and the nonzero data, it is not possible to produce the output of the zero run counter
3
x
and the output of the nonzero data in every cycle.
The prior art data processing unit has also had the problems that it lacks versatility because it is designed for performing data processing on fixed data (in the above example, data zeros), and that the processing time increases since data retrieval is performed through the entire memory even in the case of data that may be all zeros beyond a certain memory range.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an arithmetic unit with sufficient versatility to be able to not only perform the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros but also perform other processing.
It is another object of the present invention to provide an arithmetic unit with sufficient versatility to be able to not only perform the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros but also perform similar processing on data of values other than zero.
It is a further object of the present invention to provide a data processing unit that can continuously perform data processing.
It is still another object of the present invention to provide a data processing unit that can shorten the processing time required to process data.
It is yet another object of the present invention to provide a data processing unit that can increase the degree of freedom of data processing programs.
A first arithmetic unit of the present invention comprises a comparator circuit, a shifter, an adder circuit, a register, and a selection circuit. The comparator circuit takes as inputs first data as comparison reference data and second data as data to be compared with the first data, and performs a comparison between the first and the second data; when the first and the second data match as the result of the comparison, the comparator circuit outputs a value 1 and sets a match signal active, while, when the first and the second data do not match, the comparator circuit outputs the second data and sets the match signal inactive. The shifter accepts an output of the comparator circuit at its input, and shifts, or does not shift, the output of the comparator circuit, depending on the state of the match signal supplied from the comparator circuit. The adder circuit accepts an output of the shifter at one input thereof. The register accepts an output of the adder circuit at its input. The selection circuit accepts a value 0 at one input thereof and an output of the register at the other input, and couples one or the other of its inputs to the other input of the adder circuit in accordance with a selection signal.
With the selection circuit selecting either the value 0 or the output of the register in accordance with the selection signal, when the first and the second data do not match, the second data that does not match the first data is output by being paired with a count of the number of times that the second data matched the first data since the last occurrence of a mismatch between the first and the second data.
According to the above configuration, with the provision of the comparator circuit for performing a comparison between the first and second data, the shifter for accepting the output of the comparator circuit at its input, and for shifting or not shifting the output of the comparator circuit depending on the state of the match signal supplied from the comparator circuit, the adder circuit for cumulatively adding the output of the shifter, and the selection circuit, not only can the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros be performed, but similar processing can also be performed on data of values other than zero. This provides great versatility.
It is also possible to use only the function of the comparator circuit by controlling the shifter, adder circuit, and selection circuit, only the function of t

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