Arithmetic processor

Details Arithmetic processor Arithmetic processor

2006-11-07

2006-11-07

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000, C711S204000, C711S138000

Reexamination Certificate

active

07133973

ABSTRACT:
An an address generator generates a read address. It is detected whether the generated read address is continuous to the read address previously generated. A cache unit control circuit controls the read data to be directly output to a requester of the read data without passing the read data through a cache RAM, if a cache miss occurs, and if it has been detected that the two addresses are continuous. As a result, the subsequent operations can executed even if the present operation has not been completed.

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“Memory Access Cycle Enhancer”, IBM Technical Disclosure Bulletin, Dec. 1988.

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