Arithmetic logic units in series in a graphics pipeline

Details Arithmetic logic units in series in a graphics pipeline Arithmetic logic units in series in a graphics pipeline

2007-11-20

2007-11-20

Tung, Kee M. (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Logical operations

C345S506000, C345S522000

Reexamination Certificate

active

10846821

ABSTRACT:
An arithmetic logic stage in a graphics pipeline is described. The arithmetic logic stage includes a plurality of series-coupled scalar arithmetic logic units, each unit for performing an arithmetic logic operation on a set of input operands and for producing a result based thereon.

REFERENCES:
patent: 6173366 (2001-01-01), Thayer et al.
patent: 6333744 (2001-12-01), Kirk et al.
patent: 6466222 (2002-10-01), Kao et al.

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