Arithmetic circuit with overflow detection capability

Details Arithmetic circuit with overflow detection capability Arithmetic circuit with overflow detection capability

1980-11-21

1983-04-05

Malzahn, David H.

Boots, shoes, and leggings

G06F 748

Patent

active

043793380

ABSTRACT:
Overflow monitoring circuitry for an arithmetic unit offsets consecutive positive and negative overflows against one another to eliminate unnecessary overflow compensation during an arithmetic operation. In a first embodiment, an up/down counter is used to count positive overflows in one direction and negative overflows in another, with the value of the counter at the end of the arithmetic operation indicating the net overflow, if any has occurred, and the most significant bit of the counter representing the direction of any net overflow. In a second embodiment, logic circuitry offsets alternate positive and negative overflows against one another but will provide an overflow signal if either an odd number of overflows occurs or if two consecutive overflows in one direction occur during the arithmetic operation.

REFERENCES:
patent: 3700874 (1972-10-01), Heightley
patent: 3970833 (1976-07-01), Gehweiler et al.
patent: 4215415 (1980-07-01), Kanemasa et al.
patent: 4223389 (1980-09-01), Amada et al.
Drumm, "Saturation Adder Solves Overflow Problems in 2nd Order Filters" Electronic Design vol. 28, No. 18, Sep. 1, 1980, pp. 167-168.
Nguyen, "Practical Hardware Solutions for 2's Complement Arithmetic Problems" Computer Design Jul. 1979, pp. 105-112.
Ebert et al., "Overflow Oscillations in Digital Filters" The Bell System Technical Journal Nov. 1969, pp. 2999-3020.

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