Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-03-10
1999-11-23
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
G06F 1300
Patent
active
059918985
ABSTRACT:
An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme. In one embodiment, generating the pseudo-random test patterns includes multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for the peripheral devices.
REFERENCES:
patent: 4511967 (1985-04-01), Witalka et al.
patent: 4947395 (1990-08-01), Bullinger et al.
patent: 5226147 (1993-07-01), Yoshida et al.
patent: 5239262 (1993-08-01), Grutzner et al.
patent: 5369646 (1994-11-01), Shikatani
patent: 5416783 (1995-05-01), Broseghini et al.
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5617531 (1997-04-01), Crouch et al.
patent: 5724603 (1998-03-01), Nishiguchi
patent: 5790561 (1998-08-01), Broden et al.
Edirisooriya, G. et al., "Minimizing testing time in scan path architecture", IEEE Circuits and systems, 1992 Midwest Symposium, pp. 1205-1207.
N. Zacharia, J. Rajski, J. Tyszer, "Decompression of Test Data Using Variable-Length Seed LFSRs", Microelectronics and Computer Systems Laboratory, McGill University, Montreal, Canada.
S. Adham, M. Kassab, N. Mukherjee, K. Radecka, J. Rajski, J. Tyszer "Arithmetic Built-In Self Test For Digital Signal Processing Architectures", in Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, May 1-4, pp. 29.6.0-29.6.4.
J. Rajski, J. Tyszer, "On Linear dependencies in subspaces of LFSR-generated sequences", IEEE, Draft Aug. 6, 1996, pp. 0-11.
William J. Hurd, "Efficient Generation of Statiscally Good Pseudonoise by Linearly Interconnected Shift Registers", IEEE transactions on Computers, vol. c-23, No. 2, Feb. 1974, pp. 146-152.
S. Hellebrand, B. Reeb, S. Tarnick, H-J. Wunderlich, "Pattern Generation for a Deterministic BIST Scheme", 1995 IEEE, pp. 88-94.
Rajski, Tyszer, "Test Responses Compaction In Accumulators With Rotate Carry Adders", IEEE transaction on CAD of Integrated Circuits and Systems, vol. 12, No. 4, Apr. 1993.
Rajski, Tyszer, Accumulator-Based Compaction of Test Responses, IEEE Transactions on Computers, vol. 42, No. 6, Jun. 1993, pp. 643-650.
Hellebrand, Rajski, Tarnick, Venkataraman, Courtois, "Built-In test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers", IEEE transactions on Computers, vol. 44, No. 2, Feb. 1995, pp. 223-233.
Rajski Janusz
Tyszer Jerzy
Beausoliel, Jr. Robert W.
Mentor Graphics Corporation
Wright Norman Michael
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