Area-efficient VDD-to-VSS ESD protection circuit

Details Area-efficient VDD-to-VSS ESD protection circuit Area-efficient VDD-to-VSS ESD protection circuit

1996-08-15

1998-04-28

Wallace, Valencia Martin

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257355, 257360, 257361, 257363, H01L 2362

Patent

active

057448426

ABSTRACT:
An electrostatic discharge (ESD) protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, and which includes an ESD transient detection circuit connected between the VDD and VSS lines; and an electrostatic discharge circuit driven by the transient detection circuit and connected between the VDD and VSS lines, wherein the discharge circuit includes a bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein the bipolar transistor is implemented by a structure selected from a group consisting of a vertical bipolar transistor and a field oxide device, and wherein the bipolar transistor has a base that is driven by the transient detection circuit.

REFERENCES:
patent: 5255146 (1993-10-01), Miller
patent: 5440162 (1995-08-01), Worley et al.
patent: 5450267 (1995-09-01), Diaz et al.
Worley, et al., "Sub-Micron Chip ESD Protection Schemes which Avoid Avalanching Junctions," EOS/ESD Symposium, 95-13 -95-20 (1995).
Merrill, et al, "ESD Design Methodology," EOS/ESD Symposium, 93-233 -93-237, (1993).
Chatterjee, et al, "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads," IEEE Electron Device Letters, vol. 12:21-22 (Jan. 1991).
Ker, et al., "Area-Efficient CMOS Output Buffer with Enhanced High ESD Reliability for Deep Submicron CMOS ASIC," IEEE, 123-126 (Jan. 1995).
Ker, et al., ESD Protection for Deep-Submicron CMOS Technology Using Gate-Couple CMOS-Trigger Lateral Structure, IEEE, 21.2.1-21.24 (1995).

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