Area efficient delay circuits

Details Area efficient delay circuits Area efficient delay circuits

2000-05-09

2002-07-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06425115

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit design and, more particularly, to the design and use of delay circuits having increased propagation delays and minimized substrate surface area consumption.
2. Description of the Relevant Art
Integrated circuits are composed of interconnected components, such as transistors, which are fabricated onto a silicon substrate using well-known semiconductor manufacturing techniques. In today's integrated circuits, electronic signals can be transmitted at ever increasing rates of speed. Simultaneously, circuits have become increasingly smaller. While this allows the circuits to perform more quickly and more efficiently than possible when compared with previous technology, the combination of increased speed and reduced size presents several challenges for design engineers. For example, the increased speed sometimes causes signals to arrive at their intended destination at an earlier than expected time, causing the circuit to operate incorrectly.
Today's integrated circuits are very complex. In the design process, computer-aided design and computer aided engineering software tools are often employed. These tools are used to generate netlist and schematic representations of complicated integrated circuits. A netlist is a text file describing the integrated circuit. A netlist representation can be translated into a computer generated schematic representation and vice versa. Schematics often consist of cells interconnected by nets that collectively and visually demonstrate the functional design of the integrated circuit. Cells are selected from a library of cells and represent circuits consisting of logic gates. The logic gates, e.g. NOT gates (inverters), NAND gates, flip flops, buffers and the like, are themselves abstractions of more basic elements, such as transistors and resistors.
Standard cell based design is a common method for implementing computer-aided designs of integrated circuits. In standard cell based design, standard cells typically have a height that is a multiple of a standard height and a variable breadth. The breadth and the standard height are multiples of the vertical and horizontal routing grids respectively.
Timing violations, as noted above, may arise in integrated circuits when signals arrive at the wrong time and cause the circuit to function improperly. Fixing timing violations may require that a signal be delayed. One common type of timing violation is a hold time violation. Some circuits, like flip-flops, require that an input signal remain stable for a minimum time after a clock signal is received in order for that input signal to correctly propagate through the circuit. This minimum time is called the hold time. When the signal is not stable for the hold time, a hold time violation has occurred. A common way of fixing hold time violations involves placing a delay in the signal path so that the signal will remain stable during the hold time.
Area efficiency is critical in integrated circuit design—a reduction in integrated circuit area translates into higher production yields that in turn improve product profitability. One problem with adding delay elements is that they increase the amount of space required by the circuit containing them. For example, designers often insert buffer cells into a path to delay a signal. These buffer cells output the same signal that was input after a certain time period. Unfortunately, these buffer cells have been designed to have very small delays. This means that when a large delay is needed to fix a timing violation, a large number of buffers would have to be placed in the signal's path. For example, a buffer might have a delay of 200 ps and a size of 3 grids. If a delay of 2 ns is needed, 10 buffers would have to be placed in the path and these buffers would take up 30 grids.
SUMMARY OF THE INVENTION
The present invention provides a library of cells that can be stored in a computer readable memory and used in the computer-aided design of integrated circuits. Some of the cells in this cell library describe circuits having variable delays. In this cell library, two different cells are able to represent circuits that can be configured to delay signal transmission by different time periods while still being contained within substantially equal areas on a silicon substrate. One way that the cell library allows for such a configuration is if the two cells both represent a delay circuits that contains an n-channel transistor coupled to a p-channel transistor. Each n-channel and p-channel transistor has an n- or p-channel gate respectively, and this gate can be described as having a length and a width. When the length of the n-channel gate in the first delay circuit differs from the length of the n-channel gate in the second delay circuit, the delay time associated with each circuit will also differ. For example, if the length of the n-channel gate in the first circuit is longer than that of the n-channel gate in the second circuit, the first circuit can have a longer delay than the second. Furthermore, the cells may also represent a delay circuit that has a capacitor coupled to the n- and p-channel transistors. If so, the delay of the circuit can be further modified by changing the size of this capacitor. These changes in n-channel gate length and capacitor size can be made while still occupying an area on the silicon substrate that is equal or substantially equal to the area occupied by the unchanged circuit. Alternately, the library could allow designers to modify the cells such that the circuits represented by the cells differ in delay time periods and occupy areas on the substrate that differ in breadth but not in height.


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