Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-28
2001-04-17
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C365S185130, C365S185200, C365S185330, C365S103000, C365S063000
Reexamination Certificate
active
06218695
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to non-volatile memory cells. More specifically, the present invention relates to a column select circuitry for 2-bit non-volatile memory cells.
RELATED ART
FIG. 1
is a cross sectional view of a conventional 1-bit non-volatile semiconductor memory cell
10
that utilizes asymmetrical charge trapping. 1-bit memory cell
10
, which is fabricated in p-type substrate
12
, includes n+source region
14
, n+drain region
16
, channel region
17
, silicon oxide layer
18
, silicon nitride layer
20
, silicon oxide layer
22
, and control gate
24
. Oxide layer
18
, nitride layer
20
and oxide layer
22
are collectively referred to as ONO layer
21
. Memory cell
10
operates as follows. A programming operation is performed by connecting source region
14
to ground, connecting drain region
16
to a programming voltage of about 9 Volts, and connecting control gate
24
to a voltage of about 10 Volts. As a result, electrons are accelerated from source region
14
to drain region
16
. Near drain region
16
, some electrons gain sufficient energy to pass through oxide layer
18
and be trapped in nitride layer
20
in accordance with a phenomenon known as hot electron injection. Because nitride layer
20
is non-conductive, the injected charge remains localized within charge trapping region
26
in nitride layer
20
.
Memory cell
10
is read by applying 0 Volts to the drain region
16
, 2 Volts to the source region
14
, and 3 Volts to the gate electrode. If charge is stored in charge trapping region
26
(i.e., memory cell
10
is programmed), then memory cell does not conduct current under these conditions. If there is no charge stored in charge trapping region
26
(i.e., memory cell
10
is erased), then memory cell
10
conducts current under these conditions. The current, or lack of current, is sensed by a sense amplifier to determine the state of memory cell
10
.
Note that the polarity of the voltage applied across source region
14
and drain region
16
is reversed during the program and read operations. That is, memory cell
10
is programmed in one direction (with source region
14
grounded), and read the opposite direction (with drain region
16
grounded). As a result, the read operation is referred to as a reverse read operation. Memory cell
10
is described in more detail in U.S. Pat. No. 5,768,192.
Memory cell
10
can also be controlled to operate as a 2-bit non-volatile semiconductor memory cell. To accomplish this, memory cell
10
is controlled to use a second charge trapping region in nitride layer
20
, which is located adjacent to source region
14
.
FIG. 2
illustrates both the first charge trapping region
26
(described above in connection with FIG.
1
), and the second charge trapping region
28
in dashed lines. The second charge trapping region
28
is used to store a charge representative of a second bit. The second charge trapping region
28
is programmed and read in a manner similar to the first charge trapping region
26
. More specifically, the second charge trapping region
28
is programmed and read by exchanging the source and drain voltages described above for programming and reading the first charge trapping region
26
. Thus, the second charge trapping region
28
is programmed by applying 0 Volts to drain region
16
, applying 9 Volts to source region
14
and applying 10 Volts to control gate
24
. Similarly, the second charge trapping region
28
is read by applying 0 Volts to source region
14
, 2 Volts to drain region
16
, and 3 Volts to control gate
24
.
Note that because nitride layer
20
is non-conductive, the charges stored in the first and second charge trapping regions
26
and
28
remain localized within nitride layer
20
. Also note that the state of the first charge trapping region
26
does not interfere with the reading of the charge stored in the second charge trapping region
28
(and vice versa). Thus, if the first charge trapping region
26
is programmed (i.e., stores charge) and the second charge trapping region
28
is not programmed (i.e., does not store charge), then a reverse read of the first charge trapping region will not result in significant current flow. However, a reverse read of the second bit will result in significant current flow because the high voltage applied to drain region
16
will result in punch through in the channel region adjacent to first charge trapping region
26
. Thus, the information stored in the first and second charge trapping regions
26
and
28
is read properly.
Similarly, if both the first and second charge trapping regions are programmed, neither reverse read operation results in significant current flow. Finally, if neither the first charge trapping region
26
nor the second charge trapping region
28
is programmed, then both reverse read operations result in significant current flow.
Memory arrays that include 2-bit memory cells of the type described above are typically formed in blocks, each block including several 2-bit memory cells connected between parallel elongated diffused (e.g., n+) regions. The signals applied to or read from the memory cells are transmitted through the diffusion regions, which act as bit lines. A problem arises when the resistance of these diffusion bit lines affects the voltages applied to or read from the 2-bit memory cells. For example, this diffusion bit line resistance creates a back-bias effect that negatively affects programming operations. The length of the diffusion regions is limited to a relatively short length to minimize this problem (i.e., by minimizing the resistance introduced by the diffusion bit lines). However, only a limited number of memory cells can be connected to these relatively short diffusion bit lines, thereby restricting the area efficiency of the memory array architecture.
What is needed is a structure that increases the number of 2-bit memory cells that are connected to the diffusion bit lines without affecting the signals applied to or read from the 2-bit memory cells.
SUMMARY
Accordingly, the present invention provides a memory circuit (flash and EEPROM) that incorporate 2-bit non-volatile memory transistors coupled between elongated diffusion bit lines, and metal jumpers that periodically contact each elongated diffusion bit line to provide a low resistance signal path. The diffusion bit lines are connected between column select circuits that include select transistors for selectively connecting the diffusion bit lines to metal bit lines of the memory circuit. Each metal jumper extends over an associated elongated diffusion bit line, and is connected by periodically-spaced vias formed through an insulation layer located between the metal jumper and the elongated diffusion bit line.
According to one aspect of the present invention, by providing a metal jumper over each elongated diffused region, significantly longer diffusion bit lines are formed that have comparable resistance to shorter conventional (“jumperless”) diffusion bit lines. Consequently, the number of charge storage regions connected along each diffused region is significantly increased, thereby allowing a single pair of column select circuits to control a larger number of memory cells. By increasing the number of memory cells while maintaining the same number of select transistors, the area efficiency of memory arrays incorporating these longer diffusion bit lines is greatly increased over conventional (“jumperless”) arrangements.
According to another aspect of the present invention, the metal jumpers provide significantly reduced diffusion bit line resistance, thereby providing greater control over the signals applied to the memory cells. Connecting a metal jumper at both ends of a diffusion bit line reduces the resistance of the diffusion bit line. This lower resistance allows very precise control over the signals (voltages) applied to the 2-bit memory cells during programming and erasing operations. By precisely controlling these applied signals, the memory cells are able t
Bever Patrick T.
Bever Hoffman & Harms LLP
Chaudhuri Olik
Peralta Ginette
Tower Semiconductor Ltd.
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