Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2001-05-02
2002-12-03
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S691000, C257S778000, C438S612000, C438S666000
Reexamination Certificate
active
06489688
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to packaging of semiconductor devices and, more particularly, to bond pad placement for flip chip packages.
Flip chip technology provides many benefits over traditional wire bonding technologies including reduced electrical parasitics and reduced complexity in manufacturing. However, the requirements for bond pad placement for flip-chip is more stringent than for wire bonding. In particular, the pitch between bond pads for flip chip must be substantially greater than wire bond pad pitch. As shown in
FIG. 1
a,
the pitch of bond pads
10
that meets wire bonding technology rules is too small to meet flip-chip technology requirements
12
(e.g., 300 &mgr;m). This can lead to larger die sizes for the flip chip, especially for pad-limited designs where the die area is governed by the number and size of the I/O pads
16
.
Prior solutions include moving alternating bond pads further away from I/O drivers or pads
16
until the minimum bond pad spacing requirements are met, as illustrated in
FIG. 1
b.
This approach increases the die size. For example, in the flip chip technology where the bond pad pitch requirement is 300 &mgr;m, the traditional approach would be to move alternating bond pads out approximately (300 &mgr;m+bond pad height) per side.
To illustrate the die size increase, consider a chip with periphery I/O drivers which is 5000 &mgr;m per side (excluding bond pads), with a bond pad which is 80 &mgr;m in height, and which is to use flip chip package technology. Using prior techniques, there will be two rows of bond pads around the chip. The first row will be placed closest to the periphery I/O drivers, and the second row will be approximately 300 &mgr;m further from the I/O drivers. This leads to a die size of approximately, (5000 &mgr;m+80 &mgr;m (bond pad height)+300 &mgr;m)
2
, which is 5380 &mgr;m per side. This bond pad placement is inefficient since there is substantial “wasted” area around the periphery of the die.
BRIEF SUMMARY OF THE INVENTION
Embodiments of the present invention provide flip-chip bond pad arrangements that lead to a smaller increase in die size than conventional approaches. This is accomplished by using the core side of the I/O pad ring for placing some of the bond pads in order to meet the bond pad pitch requirements of flip chip technology. For example, alternating bond pads are moved inward to the core side of the I/O pads or drivers, to meet the bond pad pitch requirement between the bond pads that are moved to the core side as well the bond pads that remain outside of the core. Because the bond pads are moved inward instead of outward, the increase in the die size from the edge of the I/O pad ring is reduced.
In accordance with an aspect of the present invention, an integrated circuit device comprises a plurality of I/O pads disposed along a periphery of a core. The core has no I/O pads disposed therein. A plurality of bond pads are provided for the I/O pads. A portion of the bond pads are disposed inside the core and a remaining portion of the bond pads are disposed outside of the core.
In some embodiments, the bond pads are spaced from each other by a minimum bond pad pitch. The minimum bond pad pitch between bond pads is 300 &mgr;m. Each bond pad is disposed adjacent a corresponding I/O pad. Alternating bond pads are disposed inside the core and remaining alternating bond pads are disposed outside of the core. The I/O pads are oriented transverse to the periphery of the core.
In accordance with another aspect of the present invention, an integrated circuit device comprises a plurality of I/O pads disposed and oriented along a periphery of a core. A plurality of bond pads are provided for the I/O pads. Each bond pad is bonded on top of an active circuitry of a corresponding I/O pad. The bond pads are spaced along the periphery of the core by a minimum bond pad pitch.
In specific embodiments, the minimum bond pad pitch may be 300 &mgr;m. Each bond pad has a bond pad height which matches a height of the corresponding I/O pad to which the bond pad is bonded. A plurality of power buses extend along the I/O pads parallel to the periphery of the core. The core has no I/O pads disposed therein.
In some embodiments, the plurality of I/O pads are arranged into a plurality of rows of I/O pad rings around the periphery of the core. In one embodiment, a plurality of power buses extend along the I/O pad rings parallel to the periphery of the core. In another embodiment, a plurality of power buses extending across the I/O pad rings and across the core. The power buses provide power to both the core and the I/O pads.
In accordance with another aspect of the invention, an integrated circuit device comprises a plurality of I/O pads disposed along and oriented transverse to a periphery of a core. The I/O pads are spaced from each other by spacings in a direction along the periphery of the core. A plurality of bond pads are provided for the I/O pads. The bond pads are disposed in the spacings between the I/O pads.
In specific embodiments, the I/O pads and bond pads are alternately disposed along the periphery of the core. The bond pads are spaced from each other by a minimum bond pad pitch. The minimum bond pad pitch is 300 &mgr;m. The core has no I/O pads disposed therein.
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patent: 5581109 (1996-12-01), Hayashi et al.
patent: 5610417 (1997-03-01), Doi
patent: 5641978 (1997-06-01), Jassowski
patent: 6093942 (2000-07-01), Sei et al.
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Baumann Doug
Pandula Louis
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