Area array type semiconductor package fabrication method

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S106000, C438S111000, C438S112000, C438S118000, C438S119000, C438S123000, C438S124000, C438S125000, C438S126000, C438S127000, C438S613000, C257S667000, C257S668000, C257S669000, C257S670000, C257S671000, C257S673000, C257S674000, C257S676000, C257S773000, C257S778000, C257S787000

Reexamination Certificate

active

07122401

ABSTRACT:
An area array type semiconductor package includes a plurality of conductive media such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhesive, and a predetermined area of the lead frame and the semiconductor chip are packaged with a molding resin. Leads of the lead frame are then trimmed and formed so that the lead frame, to which the semiconductor chip is adhered, acts as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates a high temperature heat. Also, because conductive media such as solder bumps or solder balls can be used to directly connect bond pads of the chip to conductive regions of a circuit board, a size of the semiconductor package can be minimized, the arrangement of the bonding pads on the chip can be easily planned, and electrical characteristics of the semiconductor package can be improved.

REFERENCES:
patent: 5053852 (1991-10-01), Biswas et al.
patent: 5157480 (1992-10-01), McShane et al.
patent: 5182631 (1993-01-01), Tomimuro et al.
patent: 5197183 (1993-03-01), Chia et al.
patent: 5241133 (1993-08-01), Mullen, III et al.
patent: 5253010 (1993-10-01), Oku et al.
patent: 5343076 (1994-08-01), Katayama et al.
patent: 5348214 (1994-09-01), Nishiguchi et al.
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5387554 (1995-02-01), Liang
patent: 5666003 (1997-09-01), Shibata et al.
patent: 5703406 (1997-12-01), Kang
patent: 5767573 (1998-06-01), Noda et al.
patent: 5790378 (1998-08-01), Chillara
patent: 5817540 (1998-10-01), Wark
patent: 5834831 (1998-11-01), Kubota et al.
patent: 5835988 (1998-11-01), Ishii
patent: 5869883 (1999-02-01), Mehringer et al.
patent: 5883439 (1999-03-01), Saitoh
patent: 5886404 (1999-03-01), You
patent: 5923954 (1999-07-01), Cho
patent: 5963796 (1999-10-01), Kim
patent: 5965936 (1999-10-01), Stave
patent: 5989940 (1999-11-01), Nakajima
patent: 5990563 (1999-11-01), Kim
patent: 6232213 (2001-05-01), King et al.
patent: 6277670 (2001-08-01), You
patent: 6374675 (2002-04-01), DePetrillo
patent: 6566164 (2003-05-01), Glenn et al.
patent: 2001/0013645 (2001-08-01), King et al.
patent: 2001/0054752 (2001-12-01), Woodworth et al.
patent: 2002/0005571 (2002-01-01), Jiang et al.
patent: 2002/0031865 (2002-03-01), Chen et al.
patent: 2003/0160321 (2003-08-01), Cloud et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Area array type semiconductor package fabrication method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Area array type semiconductor package fabrication method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Area array type semiconductor package fabrication method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3718326

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.