Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-11
2008-03-11
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11224012
ABSTRACT:
A method for optimizing area array device pin utilization and reducing the number of layers on a multilayered PCB comprising: preparing a package of BGA pin-out maps which anticipate the effect of existing fixed pins and derives the resulting optimum pin location assignment. Each pin-out map includes an indication of the best routing for circuits from a given component to be mounted to a PCB. Applying the package of pin-out maps during an area array pin assignment phase, thereby making an area array package capable of supporting the optimum routing configuration proposed by the pin-out maps. Applying the package of pin-out maps during a PCB design phase so that the optimum circuit routing to each pin is achieved, thereby completing the strategy layed out by the proposed pin-out maps, resulting in a lower number of PCB layers.
REFERENCES:
patent: 5729467 (1998-03-01), Katsumata et al.
patent: 6584608 (2003-06-01), Kumada et al.
patent: 7114132 (2006-09-01), Yaguchi
patent: 2006/0112366 (2006-05-01), Wadland et al.
Alcatel
Garbowski Leigh M.
Zegeer Jim
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