Area array air gap structure for intermetal dielectric...

Details Area array air gap structure for intermetal dielectric... Area array air gap structure for intermetal dielectric...

1998-12-21

2001-07-31

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S411000, C438S421000, C438S618000, C438S627000

Reexamination Certificate

active

06268276

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the fabrication of Integrated Circuit devices and more specifically to the formation of air gaps as a low dielectric constant material between conductor lines on the same or on different levels.
DESCRIPTION OF THE PRIOR ART
The formation of air gaps between conducting lines of high speed Integrated Circuits (IC's) is typically a combination of the deposition of a metal layer, selective etching of the metal layer to form the desired line patterns, the deposition of a porous dielectric layer or a disposable liquid layer which is then selectively removed to form the desired air-gaps.
The continuing effort to reduce the size of individual transistors and other devices commonly integrated on a semiconductor chip and to increase the density of Integrated Circuits results in a continuing reduction of the separation between conducting layers of materials. This reduction results in an increase of capacitive crosstalk between adjacent conductor lines of a semiconductor circuit, that is the voltage on the first conductor line alters or affects the voltage on the second conductor line. This alteration in voltage can cause erroneous voltage levels in the Integrated Circuit making the IC increasingly prone to faulty operation. It becomes therefore imperative to reduce the resistance capacitance (RC) time constant and the crosstalk between adjacent conducting lines.
The capacitance between adjacent conducting lines is highly dependent on the insulator or dielectric used to separate the conducting lines. Conventional semiconductor fabrication typically uses silicon dioxide as a dielectric; this has a dielectric constant of about 3.9.
The use of many of the low dielectric constant materials is not feasible due to the fact that equipment is not available to properly process the new dielectric material in various integrated circuits. Also, the chemical or physical properties of many low dielectric constant materials are usually difficult to make compatible with or integrate into conventional integrated circuit processing.
The lowest possible and therefore the ideal dielectric constant is 1.0, this is the dielectric constant of a vacuum whereas air has a dielectric constant of slightly larger than 1.0.
To reduce said capacitive coupling and reduce the capacitive crosstalk, a major objective in the design of IC's is to reduce the Dielectric Constant (k) of the insulating layer between adjacent conductor lines of semiconductor circuits. The present invention makes a significant contribution within the scope of this effort.
U.S. Pat. No. 5,792,706 (Michael et al.) shows a method of forming Air Gaps
26
between metal lines
11
by (1) patterning a dielectric layer
20
using a PR mask (e.g., reverse metal mask or a holes anywhere mask) and (2) forming a capping dielectric layer
32
thereover to close up the air gaps. This patent appears to show the invention. See claim
1
, see
FIG. 7
;
FIGS. 1-9
; See col. 6, lines 11 to 56. Michael appears to show the invention's (a) modified reverse metal mask, see
FIGS. 8 and 9
, and a “holes everywhere” mask, see
FIG. 4
,
6
, and
7
. This patent is claimed broadly.
U.S. Pat. No. 5,324,683 (Fitch et al.), U.S. Pat. No. 5,407,860 (Stotlz et al.) and U.S. Pat. No. 5,461,003 (Havemann et al.) and U.S. Pat. No. 5,599,745 (Reinberg) show methods to form air gaps.
U.S. Pat. No. 5,750,415 (Gnade et al.) U.S. Pat. No. 5,792,706 (Michael et al.) and U.S. Pat. No. 5,407,860 (Stotz et al.) show air gap processes.
SUMMARY OF THE INVENTION
The principle object of the present invention is to provide and effective and manufacturable method of forming air gaps between conductive layers of material.
Another objective of the present invention is a method of reducing the dielectric constant k between conductive layers of material.
Another objective of the present invention is a method of reducing capacitive coupling between conducting layers of material.
Another objective of the present invention is a method of reducing capacitive crosstalk between conductive layers of material.
Another objective of the present invention is to reduce the potential for false or incorrect logic levels of the circuits in the IC's.
Another objective of the present invention is a method of reducing Resistance Capacitance delays of the circuits in the IC's.
Another objective of the present invention is to increase Switching Speed of the circuits in the IC's.
In accordance with the objects of the present invention a new method of forming air gaps between adjacent conducting lines of a semiconductor circuit is achieved. Key to the present invention is the use of a “holes everywhere” mask that can be used to create holes in a dielectric layer via standard etching techniques. The dielectric that is being etched has been deposited as a layer across the metal or conducting lines, the holes that are being formed in this manner can be closed of by a high pressure or high temperature Chemical Vapor Deposition process. The highlighted holes can be etched across the entire layer of the deposited dielectric or, if the “holes everywhere” mask is used in combination with a reverse metal mask, can be etched in between the metal or conducting lines.


REFERENCES:
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5407860 (1995-04-01), Stoltz et al.
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5599745 (1997-02-01), Reinberg
patent: 5750415 (1998-05-01), Gnade et al.
patent: 5792706 (1998-08-01), Michael et al.

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