Architectures for computer systems having multiple processors, m

Details Architectures for computer systems having multiple processors, m Architectures for computer systems having multiple processors, m

1991-09-16

1994-10-25

Chan, Eddie P.

Boots, shoes, and leggings

395200, 364DIG1, 3642582, 3642402, 364244, 3642419, G06F 1300

Patent

active

053597150

ABSTRACT:
Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

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