Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2001-12-28
2004-11-16
Pham, Chi (Department: 2667)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S236000
Reexamination Certificate
active
06819675
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the transmission of data packets such as ATM packets between Local Area Networks (LAN) interconnected by a switch engine and relates in particular to a data transmission system including a self-route multi-memory packet switch having means for processing data overflow.
2. Background of the Invention
Local Area Networks (LAN) such as Ethernet or token-ring networks, are generally interconnected through hubs. The hub is a system made of LAN adapters that communicate together through a switch card containing a switch engine. Such a switch engine can be either a shared memory switch or a crossbar switch.
The shared memory switch is a device wherein the packets received by the input ports are stored into a memory at locations the addresses of which are determined by queues containing the packet destination addresses, the packets being transmitted on the output ports as the destination addresses are dequeued. Although such a switch enables a very low cell-lost rate, it presents a bottleneck due to the requirement of the memory bandwidth, the segregation of the buffer space and the centralized control of the buffer which causes the switch performance to degrade as the size of the switch increases. A traditional approach to design a large shared memory switch has been to first design a feasible size shared memory switch and then to interconnect a plurality of such modules in order to build a large switch. This general scheme of switch growth is known to cause degradation in performance of shared memory architecture as the switch grows in size insofar as the memory access controller will have to increase the number of all centralized control functions and memory operations thereby reducing drastically the access to the shared memory. A growable switch approach packet switch architecture is a plurality of shared memory switches organized in a single stage preceded by a buffer-less interconnection network. This approach does not allow global sharing of memory space along all of its inputs and outputs. It is known that this approach does not provide the best buffer utilization as possible for a buffer belonging to a group of output ports to overflow under unbalanced or bursty traffic conditions.
The other technique, the crossbar switch, does not use a shared memory to store the data packets. In such a switch, the data are stored in the adapters and the switching data connection is established by sending requests to a control module which determines whether it is possible to satisfy the requests taking into account an algorithm defining the best data connection to establish at each time.
BRIEF SUMMARY OF THE INVENTION
The main drawback of the prior art is that the use of a centralized control module which must know the complete switching topology of the system can become impossible to control when the switch grows in size. The growth in size and therefore the increase in the number of input and output ports requires redesign of the centralized control module. Furthermore, it is impossible with this approach to achieve a speed expansion without redesigning the centralized control module.
There is a problem occurring in a switch engine when too many data packets are transmitted by an adapter. Such a problem results in a real difficulty to process the data being stored in the memory in a shared memory switch or to process the requests in a crossbar switch. In such a case the solution is to regulate the internal traffic by setting memory filling thresholds and to generate backpressure signals to the adapter so that it decreases its data flow rate. But, this requires that the thresholds being set are correctly adapted to enable the generation of the backpressure signals without loss of data occurring during the period of time between the instant when the threshold has been exceeded and the instant when the adapter has decreased its flow rate.
Accordingly, the main object of the invention is to provide a packet switch wherein there is a mechanism enabling to process the data overflow without loss of data and avoiding as much as possible the use of backpressure signals.
The invention relates therefore to a data transmission system comprising a plurality of Local Area Networks (LANs) interconnected by a hub including the same plurality of LAN adapters respectively connected to the LANs and a packet switch comprising at least a packet switch module interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded. The packet switch comprises a plurality of input ports and a same plurality of output ports both being respectively connected to the LAN adapters, each couple of an input port and an output port defining a crosspoint at which is located a memory block for storing any data packet received from the input port corresponding to the crosspoint and which is to be forwarded to the output port corresponding to the crosspoint. The system comprises a memory control means associated with each memory block within the packet switch for detecting an overflow, regulating means for preventing a further data packet from being stored in the memory block which overflows in response to the memory control block, and an overflow bus for carrying the data packet to another memory block which does not overflow, the memory block corresponding to the same output port as the memory block which overflows.
REFERENCES:
patent: 5455820 (1995-10-01), Yamada
patent: 5467347 (1995-11-01), Petersen
patent: 5570348 (1996-10-01), Holden
patent: 5689500 (1997-11-01), Chiussi et al.
patent: 5787072 (1998-07-01), Shimojo et al.
patent: 6349097 (2002-02-01), Smith
Allayer Communications, “Application Brief: Allayer Rox Bus Architecture”, Aug. 1998, www.arl.wustl.edu/~jst/cse/577/docs/allayer.pdf.
Benayoun Alain
Michel Patrick
Toubol Gilles
Canale Anthony J.
Lam Daniel K.
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