Architecture that converts a half-duplex bus to a...

Details Architecture that converts a half-duplex bus to a... Architecture that converts a half-duplex bus to a...

2005-09-13

2005-09-13

Lefkowitz, Sumati (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

C710S305000

Reexamination Certificate

active

06944691

ABSTRACT:
An architecture comprising a first circuit, a second circuit, and one or more pairs of communication channels. The first circuit may be configured to transmit one or more first serial streams in response to a plurality of first source data streams and recover a plurality of second source data streams from one or more second serial streams. The second circuit may be configured to transmit the one or more second serial streams in response to the plurality of second source data streams and recover the plurality of first source data streams in response to the one or more first serial streams. The first circuit and the second circuit may be coupled by the one or more pairs of communication channels. The first and second circuits may be configured to transmit simultaneously.

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Gabriel Li, “Circuitry, Architecture and Method(s) for Synchronizing Data”, U.S. Ser. No. 09/391,865, filed Sep. 8, 1999.

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