Architecture providing isochronous access to memory in a system

Details Architecture providing isochronous access to memory in a system Architecture providing isochronous access to memory in a system

1998-12-18

2000-08-08

Palys, Joseph E.

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

710 54, 710 61, G06F 104

Patent

active

061016136

ABSTRACT:
An architecture is provided for isochronous access to memory in a system in which a stream of information may be sent to a memory unit. The stream is divided into a plurality of service periods with a specified maximum amount of information in selected service periods, and selected service periods have a first amount of information associated with asynchronous information and a second amount of information associated with isochronous information. In addition to sending a stream of information, a request for isochronous information from the memory unit may be sent. In this case, a stream of the requested information may be received from a memory unit a predetermined number of service periods after the sending of the request. This stream is also divided into a plurality of service periods with a specified maximum amount of information in selected service periods, and each service period has a first amount of information associated with asynchronous information and a second amount of information associated with isochronous information. In either case, the second amount of information may contain asynchronous information when less than all of the second amount of information is used for isochronous information.

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