Architecture of reconfigurable radio processor

Details Architecture of reconfigurable radio processor Architecture of reconfigurable radio processor

2006-08-22

2006-08-22

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

System configuring

C710S240000, C710S100000, C455S090200

Reexamination Certificate

active

07096288

ABSTRACT:
A reconfigurable radio processor comprises a task interface and an execution kernel. The processor can be applied to a platform comprising a main processor and on-chip bus, and uses a task-based interface between the main processor and the radio processor. The radio processor simplifies the designs for control system, instruction set and data path. The bus interface includes a task dispatcher. The execution kernel comprises a global control unit, at least one function unit, an operation network, and a data network. The radio processor meets the reconfigurable and scalable requirements. It allows system designers to realize many applications on an IC chip, as well as increases the add-on values for the product. It provides system designers with the possibility of replacing another main processor under a special consideration.

REFERENCES:
patent: 5790817 (1998-08-01), Asghar et al.
patent: 2006/0035603 (2006-02-01), Al-Adnani
patent: WO 00/69084 (2000-11-01), None
“A Re-Configurable Architecture—Radio Processor” found in 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No. 03TH8672) ,p. 200-3, Hsinchu, Taiwan, Oct. 6-8, 2003. Authors: I-Tao-Liao, Tse-Hao-Lee, Chung-Chieh-Kang, Chia-Hung-Shih, Jia-Cheng-Tsai, Hung-Chi-Lai, Jian-Hui-Shen, Chi.

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