Architecture of realizing balance of bit line sense amplifier in

Details Architecture of realizing balance of bit line sense amplifier in Architecture of realizing balance of bit line sense amplifier in

1991-02-12

1993-10-19

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365214, G11C 1140

Patent

active

052552314

ABSTRACT:
The present invention provides an architecture of a DRAM cell array having a plurality of bit lines and word lines. The word lines are formed by arranging metal word lines on poly-silicon word lines in parallel, and two bit lines construct a column. The metal word lines and the poly-silicon word lines are contacted to each other every predetermined column. The contacts form metal shunted areas of word lines in a high bit density semiconductor device. In the present invention, the two bit lines that are located in the vicinity of metal shunted area are conjoined together in order to construct a column, and the column is connected to a bit line sense amplifier.

REFERENCES:
patent: 3942164 (1976-03-01), Dunn
patent: 4916661 (1990-04-01), Nawaki et al.

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