Architecture of high speed synchronous state machine

Details Architecture of high speed synchronous state machine Architecture of high speed synchronous state machine

1989-10-31

1991-06-11

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307468, 307480, H03K 19177

Patent

active

050234846

ABSTRACT:
An improved architecture for and a method of operating a high speed synchronous state machine is disclosed having a programmable logic array receiving inputs from dedicated input registers and having an input/output macrocell which includes two state registers and two input registers, and two transparent latches and two feedback multiplexers. The outputs from the input registers are multiplexed through an input multiplexer and the input registers may be clocked at different input clock rates than the state clock which clocks the state registers.

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