Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-05-28
2002-07-23
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06424986
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to signal processing, and more particularly to an architecture for performing discrete wavelet transformation (DWT) in a very large scale integration (VLSI) architecture design.
2. Description of Related Art
In the past years, there has been an enormous increase in the applications of wavelets scientific disciplines. One of the main contributions of wavelet theory is related to the discrete-time filterbank with the theory of continuous time function space. Typical applications of wavelets include signal processing, image processing, numerical analysis, statistics, biomedicine, and so on. Wavelet transform offers a wide variety of useful features, in contrast to other transforms, such as Fourier transform or cosine transform.
Since discrete wavelet transform (DWT) needs intensive computations, several solutions using special purpose parallel processors have been proposed, such as published papers, IEEE Trans., 1993, VLSI System-1, (2), pp. 191-202, IEEE Trans., 1995 SP-43, (3), pp. 759-771, and IEEE Trans., 1996, VLSI System-4, (4), PP. 421-433. In these solutions, DWT usually is based on a recursive pyramid algorithm (RPA) so as to output results in a real-time way, in which the pyramid algorithm (PA) is originally developed by S. Mallat on IEEE Trans. Acoust., speech signal processing (37) no. 12 pp. 2091-2110, 1989. However, the typical solutions with the RPA method are not effective to a wavelet packet transform (DWPT).
The RPA includes two basic transformation eqs. 1.a and 1.b:
c
j
+
1
,
m
=
∑
k
h
k
-
2
m
c
j
,
k
,
(1.a)
d
j
+
1
,
m
=
∑
k
g
k
-
2
m
c
j
,
k
,
(1.b)
where c
j,k
is the k-th scale coefficient at a decomposition level j, and d
j,k
is the k-th wavelet coefficient at the decomposition level j. With respect to the eqs. 1.a and 1.b,
FIG. 1
is a schematic block diagram, schematically illustrating a typical computation method for a three-stage DWT decomposition using RPA. In
FIG. 1
, c
0
(c
0,k
) is an initial input, c
j,k
are scale coefficient, and d
j,k
are wavelet coefficients. H and G are the filters corresponding to the scale function and wavelet function, respectively. The downward arrow means retaining every other sample. Each filter output is decimated by a factor of 2.
This leads to the fact that the transformation is implemented recursively with the same filters G and H, and that the structures are greatly dependent on the used filters. If the length of the filter is long, the architectures are inefficient and cannot be suitably implemented in a single chip because of their scale size. Particularly, the current typical architectures are not effective to the DWPT to achieve a real-time computation.
SUMMARY OF THE INVENTION
It is at least an objective of the present invention to provide an address generator to produce a specified coefficient sequence incorporating with a DWT/DWPT architecture so as to improve the computation efficiency, in which two buffer memory system is also employed.
It is at least another objective of the present invention to provide a wavelet transformation architecture, which has high computational efficient and can be easily fabricated in a single integrated circuit (IC) chip or an on-chip structure.
In accordance with the foregoing and other objectives of the present invention, an address generator to produce a data sequence with a binary bit-reverse order, suitable for use in a discrete wavelet transform (DWT) or a discrete wavelet packet transform (DWPT) is provided. The address generator comprises a bit-reverse unit for receiving a frequency band index and generate the bit-reverse order of the band index. The address generator further includes a DFF unit serving as a latch, a multiplexer, controlled by a control signal, for receiving outputs from the bit-reverse unit and the DFF unit and selectively exporting one of them. A frequency band base unit is also included for receiving a decomposition level j so as to produce a base number of 2
j
. The address generator further comprises an adder for receiving base number and the multiplexer and exporting an address. The address is also feedback to the DFF unit so that the data sequence with the binary bit-reverse order is obtained.
As the control signal CTRL is at a first logic level, the address generator is set to start a new frequency band, in which the multiplexer selects the output from the bit-reverse unit. As the control signal CTRL is at a second logic level, the address generator is set to generate rest internal address in the same frequency index, in which the multiplexer selects a previous content stored in the latch unit and the previous content is added with the base number of 2
j
. Therefore, a regular data sequence is rearranged into a bit-reverse data sequence.
In the above address generator of the invention, the decomposition level j can orderly vary from 0 up to a desired level J or vary from the desired level J to 0 so as to respectively perform the DWT or the DWPT forwardly and inversely.
The address generator can generate the data sequence with the special bit-reverse order and can be used in a DWT/DWPT operation. For example, the address generator is included in a two-buffer system for the DWT or the DWPT to perform a real-time DWT/DWPT. The two-buffer system can include two buffers, which are alternating their functions in an operation time frame with a frame length of N, which is an integer. If one of the buffers is used for storing input data and exporting results, the other one of the buffers is used for performing transform, in which the data sequence in each of the buffers is based on the address generator.
The two-buffer system includes an address switch, which receives an address input/output (I/O) and an address for transform. Then, address switch initially switches the buffers and passes the received addresses to the buffers.
Moreover, the two-buffer system includes a data switch that is used to alternatingly switch the buffers so as to recursively communicate with an I/O unit and an process unit in the real-time DWT/DWPT. Each of the buffers has a length equal to the frame length.
In accordance with the foregoing and other objectives of the present invention, a very large scale integration (VLSI) wavelet transform (WT) architecture suitable for use in a discrete wavelet transform (DWT) or a discrete wavelet packet transform (DWPT) is provided. The WT architecture includes a multiplier, an accumulator, at least two address generators, which comprises a first address generator and a second address generator, a control unit, a memory of result, which stores computation results, and a memory of table.
The memory of table pre-stores a plurality of weights of all possible filter coefficient products for performing a DWT/DWPT with parameters of J, N, and L, respectively representing a decomposition level, a length of data segment, and a filter length.
In the WT architecture, the first address generator and the control unit receive a data input, the control unit exports control signals to the multiplier, the accumulator, the second address generator, and the memory of the table. The memory of the table also receives outputs from the first address generator and the second address generator to select the desired weights of the filter coefficient product, which are sent to the multiplier to obtain a product of the desired weight of the filter coefficient product. The product is sent to the accumulator to add into a corresponding sum. The memory of result receives the corresponding sum and an address output of the second address generator to address the received corresponding sum. When all of the data input in the DWT/DWPT are completely inputted, each the corresponding sum is an end result of the DWT/DWPT.
The control signals from the control unit to the multiplier at least includes a first signal and a second signal. The first signal intermediately enters a first DFF unit and a demultiplexer and the second signal dire
Chen Hongyi
Li Yongming
Wu Xiaodong
J. C. Patents
Mai Tan V.
Winbond Electronics (H.K.) Ltd.
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