Architecture of a phase-change nonvolatile memory array

Details Architecture of a phase-change nonvolatile memory array Architecture of a phase-change nonvolatile memory array

2002-12-12

2004-11-09

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Amorphous

C365S174000, C365S175000

Reexamination Certificate

active

06816404

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the architecture of a phase-change nonvolatile memory array.
2. Description of the Related Art
As is known, phase-change memory (PCM) arrays are based on storage elements that use a class of materials which have the property of changing between two phases having distinct electrical characteristics. For example, these materials may change from an amorphous, disorderly phase to a crystalline or polycrystalline, orderly phase, and the two phases are associated to considerably different values of resistivity.
At present, alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can advantageously be used in phase-change cells. The chalcogenide that currently offers the most promise is formed by a Ge, Sb and Te alloy (Ge
2
Sb
2
Te
5
) and is widely used for storing data in overwritable disks.
In chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous phase (more resistive) to the crystalline phase (more conductive) and vice versa. The characteristics of the chalcogenides in the two phases are shown in FIG.
1
. As may be noted, at a given read voltage, here designated by Vr, there is a variation in resistance of more than 10.
Phase change may be obtained by locally increasing the temperature, as shown in FIG.
2
. Below 150° C. both phases are stable. Above 200° C. (nucleation starting temperature, designated by T
x
), there takes place fast nucleation of the crystallites, and, if the material is kept at the crystallization temperature for a sufficient length of time (time t
2
), it changes its phase and becomes crystalline. To bring the chalcogenide back into the amorphous state, it is necessary to raise the temperature above the melting temperature T
m
(approximately 600° C.) and then to cool the chalcogenide off rapidly (time t
1
).
From the electrical standpoint, it is possible to reach both the critical temperatures, namely the crystallization temperature and the melting point, by causing a current to flow through a resistive element which heats the chalcogenic material by the Joule effect.
The basic structure of a phase-change storage element
1
which operates according to the principles described above is shown in FIG.
3
and comprises a resistive element
2
(heater) and a programmable element
3
. The programmable element
3
is made with a chalcogenide and is normally in the crystalline state in order to enable a good flow of current. One part of the programmable element
3
is in direct contact with the resistive element
2
and forms a phase-change portion
4
.
If an electric current having an appropriate value is made to pass through the resistive element
2
, it is possible to heat the phase-change portion
4
selectively up to the crystallization temperature or to the melting temperature and to cause phase change.
The state of the chalcogenic material can be measured by applying a sufficiently small voltage, such as not to cause a sensible heating, and by then reading the current that is flowing. Given that the current is proportional to the conductivity of the chalcogenide, it is possible to discriminate wherein state the chalcogenide is.
Of course, the chalcogenide can be electrically switched between different intermediate states, thus affording the possibility of obtaining a multilevel memory.
In practice, a phase-change memory element or PCM storage element
1
can be considered as a resistor which conducts a different current according to its phase. In particular, the following convention is adopted: a phase-change storage element is defined as “set” when, once it is appropriately biased, it conducts a detectable current (this condition may be associated to a logic condition “1”) and as “reset” when, in the same biasing conditions, it does not conduct current or conducts a much lower current than that of a cell that is set (logic condition “0”).
The use of PCM storage elements has already been proposed in memory arrays formed by a plurality of memory cells arranged on rows and columns. In order to prevent the memory cells from being affected by noise caused by adjacent memory cells, generally each memory cell comprises a PCM storage element of the type described above and a selection element, such as a MOS transistor or a diode, in series to the PCM storage element.
When the selection element is a diode, each cell is connected at the intersection of two selection lines, perpendicular to one another, one of which is parallel to the rows of the memory array, while the other is parallel to the columns.
When the selection element is a transistor, different solutions are known which are essentially based upon biasing the source terminal of the selection element at variable voltages that depend upon the reading or programming operation (set, reset) of the memory. For example, according to U.S. Pat. No. 6,314,014, a first terminal of the PCM storage element is biased at a biasing voltage the value of which depends upon the operation (either reading or programming) of the cell, a second terminal of the PCM storage element is connected to a drain terminal of the selection transistor, the gate terminal of the selection transistor is connected to a row line, and the source terminal of the selection transistor is connected to a column line. In practice, selection of the cell takes place via the source and gate terminals of the selection transistor. Alternatively, the drain terminal of the selection transistor can be biased at the biasing voltage, and the memory cell
1
can be coupled between the source terminal and its own column line.
All the above known solutions thus entail biasing of three different terminals of the cell, and hence special biasing lines, which complicate the circuits associated to the memory array. In addition, on account of the non-zero biasing of the source region, there is a sensible body effect, which determines an increase in the threshold voltage of the selection transistor, and hence of the voltage that is to be generated and fed within the memory, of course involving additional costs.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention provides an architecture for phase-change memory arrays which will overcome the disadvantages of the prior art solutions.
An embodiment of the present invention is directed to a phase-change nonvolatile memory array formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.


REFERENCES:
patent: 4599705 (1986-07-01), Holmberg et al.
patent: 4876668 (1989-10-01), Thakoor et al.
patent: 5801983 (1998-09-01), Saeki
patent: 5883827 (1999-03-01), Morgan
patent: 5898619 (1999-04-01), Chang et al.
patent: 6314014 (2001-11-01), Lowrey et al.
patent: 6590807 (2003-07-01), Lowrey
patent: 6673648 (2004-01-01), Lowrey

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